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W9864G6GB

1M × 4 BANKS × 16 BITS SDRAM

Publication Release Date: August 14, 2006

- 1 - Revision A01

Table of Contents-

1. GENERAL DESCRIPTION.............................................................................................................3

2. FEATURES .................................................................................................................................... 3

3. AVAILABLE PART NUMBER......................................................................................................... 3

4. PIN CONFIGURATION .................................................................................................................. 4

5. PIN DESCRIPTION........................................................................................................................ 5

6. BLOCK DIAGRAM ......................................................................................................................... 6

7. FUNCTIONAL DESCRIPTION....................................................................................................... 7

7.1 Power Up and Initialization.................................................................................................. 7

7.2 Programming Mode Register .............................................................................................. 7

7.3 Bank Activate Command ..................................................................................................... 7

7.4 Read and Write Access Modes ........................................................................................... 7

7.5 Burst Read Command......................................................................................................... 8

7.6 Burst Command...................................................................................................................8

7.7 Read Interrupted by a Read ................................................................................................ 8

7.8 Read Interrupted by a Write ................................................................................................ 8

7.9 Write Interrupted by a Write ................................................................................................ 8

7.10 Write Interrupted by a Read ................................................................................................ 8

7.11 Burst Stop Command .......................................................................................................... 9

7.12 Addressing Sequence of Sequential Mode ......................................................................... 9

7.13 Addressing Sequence of Interleave Mode .......................................................................... 9

7.14 Auto-precharge Command ................................................................................................ 10

7.15 Precharge Command ........................................................................................................ 10

7.16 Self Refresh Command ..................................................................................................... 10

7.17 Power Down Mode ............................................................................................................ 11

7.18 No Operation Command ................................................................................................... 11

7.19 Deselect Command........................................................................................................... 11

7.20 Clock Suspend Mode ........................................................................................................ 11

8. TABLE OF OPERATING MODES ............................................................................................... 12

8.1 Simplified State Diagram................................................................................................... 13

9. ABSOLUTE MAXIMUM RATING ................................................................................................. 14

10. RECOMMENDED DC OPERATING CONDITIONS .................................................................... 14

Summary of content (47 pages)

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W9864G6GB 1M × 4 BANKS × 16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION............................................................................................................. 3 2. FEATURES .................................................................................................................................... 3 3. AVAILABLE PART NUMBER......................................................................................................... 3 4. PIN CONFIGURATION ...............
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W9864G6GB 11. CAPACITANCE............................................................................................................................ 14 12. DC CHARACTERISTICS ............................................................................................................. 15 13. AC CHARACTERISTICS ............................................................................................................. 16 14. TIMING WAVEFORMS ...........................................................
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W9864G6GB 1. GENERAL DESCRIPTION W9864G6GB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words × 4 banks × 16 bits. Using pipelined architecture and 110nm process technology, W9864G6GB delivers a data bandwidth of up to 286MHz bytes per second (-7). The -7 parts can run up to 143MHz/CL3. Accesses to the SDRAM are burst oriented.
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W9864G6GB 4.
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W9864G6GB 5. PIN DESCRIPTION BALL LOCATION PIN NAME FUNCTION M1,M2,N1,N2,N6, N7,P1,P2,P6,P7, R6, A0−A11 Address M6,M7 BS0, BS1 Bank Select DESCRIPTION Multiplexed pins for row and column address. Row address: A0−A11. Column address: A0−A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. Select bank to activate during row address latch time, or bank to read/write during address latch time.
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W9864G6GB 6.
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W9864G6GB 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VCC +0.
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W9864G6GB 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.
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W9864G6GB 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
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W9864G6GB 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
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W9864G6GB 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK.
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W9864G6GB 8. TABLE OF OPERATING MODES Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.
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W9864G6GB 8.
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W9864G6GB 9. ABSOLUTE MAXIMUM RATING PARAMETER SYM. RATING UNIT NOTES Input, Column Output Voltage(-7) VIN, VOUT 2.7V~3.6V V 1 Power Supply Voltage VCC, VCCQ -0.3 − 4.
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W9864G6GB 12. DC CHARACTERISTICS (VCC=2.7V~3.6V, TA = 0 to 70°C ) PARAMETER Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: Inactive State SYM. -7 ( MAX.) UNIT NOTES ICC1 80 3 ICC2 30 3 ICC2P 2 3 ICC2S 15 1 bank operation CKE = VIH CKE = VIL (Power Down mode) Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.
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W9864G6GB 13. AC CHARACTERISTICS (VCC = 2.7V~3.6V, VSS = 0V,TA = 0 to 70°C ) (Notes: 5, 6.) PARAMETER Ref/Active to Ref/Active Command Period SYM. -7 MIN. MAX.
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W9864G6GB Notes: 1. Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the devices. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of Tck and Trc. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up Sequence (1) Power up must be performed in the following sequence.
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W9864G6GB (2) A.
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W9864G6GB 14. TIMING WAVEFORMS 14.
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W9864G6GB 14.
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W9864G6GB 14.
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W9864G6GB 14.
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W9864G6GB 14.
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W9864G6GB 15. OPERATING TIMING EXAMPLE 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.14 Power-down Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa A0-A9 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 Active tCKS tCKS DQ NOP ax1 ax2 ax3 Precharge Read NOPActive Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low".
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 0 1 2 Read Write 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 (1) CAS Latency=2 ( a ) Command DQM DQ ( b ) Command D0 Read Write DQM DQ (2) CAS Latency=3 ( a ) Command Read D3 Write DQM D0 DQ ( b ) Command Read Write DQM DQ D0 D3 Note: The Output data must be masked by DQM to avoid I/O conflict.
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W9864G6GB 15.
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W9864G6GB 15.
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W9864G6GB 15.20 CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cycle No.
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W9864G6GB 15.21 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 5 6 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q6 Q4 Open (2) CLK cycle No.
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W9864G6GB 15.22 Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on tim e (Power down m ode exit tim e) is specified by t CKS (m in.) + t CK (m in.) A ) t CK < t CKS (m in.) + t CK (m in.) tC K CLK CKE tCKS(m in)+tCK(m in) NOP Com m and Command Input Buffer Enable B) t CK >= t CKS (m in.) + t CK (m in.
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W9864G6GB 16. PACKAGE DIMENSIONS VFBGA60Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø=0.
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W9864G6GB 17. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A01 8/14/2006 ALL CREAT NEW DATASHEET Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life.