LogiCORE IP Block Memory Generator v6.1 DS512 March 1, 2011 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE™ IP Block Memory Generator (BMG) core is an advanced memory constructor that generates area and performance-optimized memories using embedded block RAM resources in Xilinx FPGAs. Available through the CORE Generator™ software, users can quickly create optimized memories to leverage the performance and features of block RAMs in Xilinx FPGAs.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 • Supports data widths from up to 256 bits and memory depths from 2 to 9 M words (limited only by memory resources on selected part) • Symmetric aspect ratios • Asynchronous active low reset Native Block Memory Generator Feature Summary Overview The Block Memory Generator core uses embedded Block Memory primitives in Xilinx FPGAs to extend the functionality and capability of a single primitive to memories of arbitrary widths and depths.
LogiCORE IP Block Memory Generator v6.1 Table 1: Supported FPGA Families and Sub-Families (Cont’d) FPGA Family Sub-Family Virtex-5 LXT/FXT/SXT/TXT Virtex-6 CXT/HXT/LXT/SXT Virtex-7 Kintex-7 Memory Types The Block Memory Generator core uses embedded block RAM to generate five types of memories: • Single-port RAM • Simple Dual-port RAM • True Dual-port RAM • Single-port ROM • Dual-port ROM For dual-port memories, each port operates independently.
LogiCORE IP Block Memory Generator v6.1 • In Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA-based memories, the Read width may differ from the Write width by a factor of 1, 2, 4, 8, 16, or 32 for each port. The maximum ratio between any two of the data widths (DINA, DOUTA, DINB, and DOUTB) is 32:1.
LogiCORE IP Block Memory Generator v6.1 AXI4 Interface Block Memory Generator Feature Summary Overview AXI4 Interface Block Memories are built on the Native Interface Block Memories (see Figure 1). Two AXI4 interface styles are available - AXI4 and AXI4-Lite. The core can also be further classified as a Memory Slave or as a Peripheral Slave.
LogiCORE IP Block Memory Generator v6.1 All Write operations are initiated on the Write Address Channel (AW) of the AXI bus. The AW channel specifies the type of Write transaction and the corresponding address information. The Write Data Channel (W) communicates all Write data for single or burst Write operations. The Write Response Channel (B) is used as the handshaking or response to the Write operation.
LogiCORE IP Block Memory Generator v6.1 Figure 4 shows an example application for AXI4-Lite Memory Slave Interface Type with an AXI4-Lite Interconnect to manage Control/Status Accesses. The minimum memory requirement for this configuration is set to 4K bytes. Data widths of 32 and 64 bits are supported by this configuration.
LogiCORE IP Block Memory Generator v6.1 Supported Devices Table 2: AXI4 BMG Supported FPGA Families and Sub-Families FPGA Family Sub-Family Spartan-6 LX/LXT Virtex-6 CXT/HXT/LXT/SXT Virtex-7 Kintex-7 AXI4 BMG Core Channel Handshake Sequence Figure 9 and Figure 10 illustrates an example handshake sequence for AXI4 BMG core. Figure 9 illustrates single burst Write operations to block RAM.
LogiCORE IP Block Memory Generator v6.1 Figure 9 illustrates single burst Read operations to block RAM. The registered ARREADY signal output on the AXI Read Address Channel interface defaults to a high assertion. The AXI Read FSM can accept the read address in the clock cycle where the ARVALID signal is first valid. The AXI Read FSM can accept a same clock cycle assertion of the RREADY by the master if the master can accept data immediately.
LogiCORE IP Block Memory Generator v6.1 In compliance with AXI Protocol, the burst termination boundary for a transaction is determined by the length specified in the AWLEN signal. The allowable burst sizes for INCR bursts are from 1 (00h) to 256 (FFh) data transfers. X-Ref Target - Figure 11 $&/.
LogiCORE IP Block Memory Generator v6.1 accepting the Read burst data (by negating RREADY), the Read FSM handles this by holding the data pipeline until RREADY is asserted. X-Ref Target - Figure 12 $&/. $59$/,' $55($'< ;;;;;;;; K K ;;;;;;;; $5/(1> @ ;; K ))K ;; $56,=(> @ ;;; E E ;;; $5%8567> @ ;; E E ;; $5$''5> @ 59$/,' 55($'< 5'$7$ > @ ;;;;;;;; ) ) ) ) K $ $ $ K $ K $ $ $ $ K E 2.$< E 2.$< E 2.$< E 2.
LogiCORE IP Block Memory Generator v6.1 RAM will see the following sequence of addresses for Read requests: 0x04h, 0x08h, 0x0Ch, 0x00h. Note the wrap of the cache line address from 0xCh back to 0x00h at the end. X-Ref Target - Figure 13 $&/.
LogiCORE IP Block Memory Generator v6.1 Figure 14 illustrates the timing on AXI WRAP or cache line burst Read transactions. X-Ref Target - Figure 14 $&/. $59$/,' $55($'< ;;;;;;;; K ;;;;;;;; K ;;;;;;;; $5/(1> @ ;; K ;; )K ;; $56,=(> @ ;;; E ;;; E ;;; $5%8567> @ ;; E ;;; E ;; $5$''5> @ 59$/,' 55($'< 5'$7$ > @ ;;;;;;;; $ $ $ $K ;; E 2.$< $ K $ K ' ' ' ' K E 2.$< E 2.$< 5/$67 55(63> @ E 2.
LogiCORE IP Block Memory Generator v6.1 AXI4 Narrow Transactions A narrow burst is defined as a master bursting a data size smaller than the block RAM data width. If the burst type (AWBURST) is set to INCR or WRAP, then the valid data on the block RAM interface to the AXI bus will rotate for each data beat. The Write and Read FSM handles each data beat on the AXI as a corresponding data beat to the block RAM, regardless of the smaller valid byte lanes.
LogiCORE IP Block Memory Generator v6.1 Figure 16 illustrates an example of AXI “narrow” Read bursting with a 32-bit block RAM and the AXI master request is a half-word burst of 4 data beats. ARSIZE is set to 001b. X-Ref Target - Figure 16 $&/.
LogiCORE IP Block Memory Generator v6.1 something other than 0x0h, 0x4h, 0x8h, etc. The example shown in Figure 17 illustrates an unaligned word burst transaction of 4 data beats, which starts at address offset, 0x1002h. X-Ref Target - Figure 17 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Figure 17: AXI4 Unaligned Transactions For more details on AXI4 Narrow Transactions refer to the “about unaligned transfers” section of the AXI protocol specification [Ref 1].
LogiCORE IP Block Memory Generator v6.1 addressing. Table 5 illustrates some example settings to create a specific size of block RAM in the system.
LogiCORE IP Block Memory Generator v6.1 Optional Pipeline Stages Pipeline stages are currently not supported. Memory Initialization Capability The memory contents can be optionally initialized using a memory coefficient (COE) file or by specifying a default data value. A COE file can define the initial contents of each individual memory location, while the default data value option defines the initial content for all locations.
LogiCORE IP Block Memory Generator v6.1 The Dual-port ROM allows Read access to the memory space through two ports, as shown in Figure 19. X-Ref Target - Figure 19 Dual-Port ROM ADDRA DOUTA ENA RSTA REGCEA CLKA ADDRB DOUTB ENB RSTB REGCEB CLKB Figure 19: Dual-port ROM The Single-port RAM allows Read and Write access to the memory through a single port, as shown in Figure 20.
LogiCORE IP Block Memory Generator v6.1 Note: For Virtex family architectures, Read access is via port A and Write access is via port B. X-Ref Target - Figure 21 Simple Dual-Port RAM DINA ADDRA WEA SBITERR ENA DBITERR CLKA RDADDRECC INJECTSBITERR INJECTDBITERR ADDRB DOUTB ENB RSTB REGCEB CLKB Figure 21: Simple Dual-port RAM The True Dual-port RAM provides two ports, A and B, as illustrated in Figure 22. Read and Write accesses to the memory are allowed on either port.
LogiCORE IP Block Memory Generator v6.1 Selectable Memory Algorithm The Block Memory Generator core arranges block RAM primitives according to one of three algorithms: the minimum area algorithm, the low power algorithm and the fixed primitive algorithm. Minimum Area Algorithm The minimum area algorithm provides a highly optimized solution, resulting in a minimum number of block RAM primitives used, while reducing output multiplexing.
LogiCORE IP Block Memory Generator v6.1 multiplexers than the minimum area algorithm. Figure 24 shows two examples of memories built using the low power algorithm. X-Ref Target - Figure 24 3kx16 Memory 5kx17 Memory 1kx18 1kx18 1kx18 1kx18 1kx18 1kx18 1kx18 1kx18 Figure 24: Examples of the Low Power Algorithm Note: In Spartan-6 devices, two 9K block RAMs are used for one 1Kx18. Fixed Primitive Algorithm The fixed primitive algorithm allows the user to select a single block RAM primitive type.
LogiCORE IP Block Memory Generator v6.1 memory structures to enhance performance. Table 6 shows the primitives used to construct a memory given the specified architecture and primitive selection.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 The operating modes have an effect on the relationship between the A and B ports when the A and B port addresses have a collision. For detailed information about collision behavior, see Collision Behavior, page 30. For more information about operating modes, see the block RAM section of the user guide specific to the device family.
LogiCORE IP Block Memory Generator v6.1 • No Change Mode: In NO_CHANGE mode, the output latches remain unchanged during a Write operation. As shown in Figure 28, the data output is still the previous Read data and is unaffected by a Write operation on the same port.
LogiCORE IP Block Memory Generator v6.1 Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios When implementing RAMs targeting Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs, the Block Memory Generator allows Read and Write aspect ratios on either port. On each port A and port B, the Read to Write data width ratio of that port can be 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1, or 32:1.
LogiCORE IP Block Memory Generator v6.1 BW0 is made up of AW3, AW2, AW1, and AW0. In the same way, BR0 is made up of AR1 and AR0, and AW0 is made up of BR1 and BR0. In the example above, the largest data width ratio is port B Write words (256 bits) to port A Read words (16 bits); this ratio is 16:1. Aspect Ratio Limitations In general, no port data width can be wider than 1152 bits, and no two data widths can have a ratio greater than 32:1.
LogiCORE IP Block Memory Generator v6.1 Byte-Write Example Consider a Single-port RAM with a data width of 24 bits, or 3 bytes with byte size of 8 bits. The Write enable bus, WEA, consists of 3 bits. Figure 31 illustrates the use of byte-writes, and shows the contents of the RAM at address 0. Assume all memory locations are initialized to 0.
LogiCORE IP Block Memory Generator v6.1 • Using Byte-Writes. When using byte-writes, memory contents are not corrupted when separate bytes are written in the same data word. RAM contents are corrupted only when both ports attempt to Write the same byte. Figure 32 illustrates this case. Assume ADDRA = ADDRB = 0.
LogiCORE IP Block Memory Generator v6.1 define the Write-to-Read relationship of the A or B ports, and only impact the relationship between A and B ports during an address collision. For Synchronous Clocking and during a collision, the Write mode of port A can be configured so that a Read operation on port B either produces data (acting like READ_FIRST), or produces undefined data (Xs). For this reason, the core is hard-coded to produce READ_FIRST-like behavior when configured as a Simple Dual-port RAM.
LogiCORE IP Block Memory Generator v6.1 Figure 34 shows a memory configuration with registers at the output of the memory primitives and at the output of the core for one of the ports.
LogiCORE IP Block Memory Generator v6.1 For Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A DSP FPGAs, the Register Port [A|B] Output of Memory Primitives option may be implemented using the embedded block RAM registers, requiring no further FPGA resources. All other register stages are implemented in FPGA fabric.
LogiCORE IP Block Memory Generator v6.1 The pipeline stages are common for port A and port B and can be a value of 1, 2, or 3 if the Register Output of Memory Core option is selected in the GUI for both port A and port B. Note that each pipeline stage adds an additional clock cycle of latency to the Read operation. If the configuration has BuiltIn_ECC (ECC), the SBITERR and DBITERR outputs are delayed to align with DOUT.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 Optional Set/Reset Pins The set/reset pins (RSTA and RSTB) control the reset operation of the last register in the output stage. For memories with no output registers, the reset pins control the memory output latches. When RST and REGCE are asserted on a given port, the data on the output of that port is driven to the reset value defined in the CORE Generator GUI. (The reset occurs on RST and EN when the Use REGCE Pin option is not selected.
LogiCORE IP Block Memory Generator v6.1 Figure 38 depicts how REGCE can be used to latch the data output to allow only intended data through. Assume that only the memory primitive registers are used for port A, and that EN is always asserted and RST is always deasserted. The data on the block RAM memory latch is labeled latch, while the output of the last register, the block RAM embedded register, is the core output, DOUT.
LogiCORE IP Block Memory Generator v6.1 Figure 40 illustrates the reset behavior when the Reset Priority option is set to SR. Here, reset is not dependent on enable and both reset operations occur successfully.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 does not appear at the output. At the time of the third reset, only REGCEA is high; so the reset value is asserted at the output for only one clock cycle.
LogiCORE IP Block Memory Generator v6.1 • Reset Type: This option determines if the reset is synchronous or asynchronous in Spartan-6 devices. In addition to the above options, the options of output registers also affects reset functionality, since the option to reset the memory latch depends on these options. Table 8 lists the dependency of the reset behavior for Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices on these parameters. In these configurations, the core output register does not exist.
LogiCORE IP Block Memory Generator v6.1 1 1 1 1 1 1 1 X DS512 March 1, 2011 Product Specification Reset Type (Spartan-6 Only) Reset Priority for Port A Reset Memory Latch Register Port A Output of Memory Primitives Use RSTA Pin Table 8: Control of Reset Behavior in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 for Single Port S6 RESET BEHAVIOR V6 RESET BEHAVIOR Both memory latch and embedded output register of primitive are reset.
LogiCORE IP Block Memory Generator v6.1 Built-in Error Correction Capability and Error Injection For Kintex-7, Virtex-7, Virtex-6, and Virtex-5 devices, the Block Memory Generator core supports builtin Hamming Error Correction Capability (ECC) for the block RAM primitives. For device support, see Table 9. Each Write operation generates eight protection bits for every 64 bits of data, which are stored with the data in memory.
LogiCORE IP Block Memory Generator v6.1 Figure 46 illustrates a typical Write and Read operation for a Kintex-7, Virtex-7, Virtex-6, and Virtex-5 FPGA Block Memory Generator core in Simple Dual-port RAM mode with BuiltIn_ECC enabled, and no additional output registers.
LogiCORE IP Block Memory Generator v6.1 Figure 47 shows the assertion of the SBITERR and DBITERR output signals when errors are injected through the error injection pins during a Write operation.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 . Table 11: Memory Width Calculation for Selected User Data Width User Input Data Width Added Check Bits Total Memory Width in Bits 1-4 4 5-8 5-11 5 10-16 12-26 6 18-32 27-57 7 34-64 58-64 8 66-72 Figure 48 illustrates the implementation of Soft ECC logic for the Block Memory Generator core. The implementation shown in Figure 48 is for 64 bits of data; the implementation is parameterized for other data widths.
LogiCORE IP Block Memory Generator v6.1 Parameters • softecc: This parameter enables the Soft ECC logic for Kintex-7, Virtex-7, Virtex-6, and Spartan-6 device families. • register_porta_input_of_softecc: This parameter registers the input ports in the design. • register_portb_output_of_softecc: This parameter registers the output ports in the design.
LogiCORE IP Block Memory Generator v6.1 • When the use_error_injection_pins parameter is enabled and “Single_and_Double_Bit_Error_Injection” option is selected: INJECTSBITERR and INJECTDBITERR ports are made available on the IO interface X-Ref Target - Figure 49 Figure 49: GUI Page 1: Enabling Soft ECC Option 50 www.xilinx.
LogiCORE IP Block Memory Generator v6.1 X-Ref Target - Figure 50 Figure 50: GUI Page 3: Enabling Input/Output Registering Stages DS512 March 1, 2011 Product Specification www.xilinx.
LogiCORE IP Block Memory Generator v6.1 Timing Diagrams Figure 51 illustrates a typical Write and Read operation for Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices for a core with a simple dual-port RAM configuration with Soft ECC enabled and no additional input or output registers. X-Ref Target - Figure 51 CLKA, CLKB WEA DINA 2222 1111 aa ADDRA ENA aa ADDRB DOUTB 00 1100 DBITERR SBITERR ENB Figure 51: Read and Write Operations with Soft ECC 52 www.xilinx.
LogiCORE IP Block Memory Generator v6.1 Figure 52 shows the assertion of the SBITERR and DBITERR output signals when errors are injected through the error injection pins during a Write operation.
LogiCORE IP Block Memory Generator v6.1 Device Utilization and Performance Benchmarks Table 12: Resource utilization for Spartan-6 Devices (XC6SLX25T-2CSG324) (1) (2) Resource Utilization (3) Depth x Width 1Kx8 1Kx16 1Kx32 1Kx64 1. 2. 3. 4.
LogiCORE IP Block Memory Generator v6.1 Lower Data Widths in Kintex-7, Virtex-7, and Virtex-6 SDP Configurations The Kintex-7, Virtex-7, and Virtex-6 FPGA architectures with the new SDP primitives support lower data widths than the Virtex-5 FPGAs. In Virtex-5 devices, the RAMB18SDP primitive could only support a symmetric configuration with port widths of 36, and the RAMB36SDP primitive could only support a symmetric configuration with port widths of 72.
LogiCORE IP Block Memory Generator v6.1 simulation models generated. Table 15 defines the differences between the two functional simulation models.
LogiCORE IP Block Memory Generator v6.1 Table 16: Core Signal Pinout (Cont’d) Name Direction Description Output Port B Data Output: Data output from Read operations via Port B. Available in dual-port configurations. ENB Input Port B Clock Enable: Enables Read, Write, and reset operations via Port B. Optional in dual-port configurations. WEB Input Port B Write Enable: Enables Write operations via Port B. Available in Dualport RAM configurations.
LogiCORE IP Block Memory Generator v6.1 Table 18: AXI4 Write Channel Interface Signals (Cont’d) Name S_AXI_AWLEN[7:0] S_AXI_AWSIZE[2:0] S_AXI_AWBURST[1:0] S_AXI_AWVALID S_AXI_AWREADY Direction Description Input Burst Length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address. Input Burst Size. This signal indicates the size of each transfer in the burst.
LogiCORE IP Block Memory Generator v6.1 Table 18: AXI4 Write Channel Interface Signals (Cont’d) Name S_AXI_BRESP[1:0] S_AXI_BVALID S_AXI_BREADY Direction Description Output Write Response. This signal indicates the status of the Write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR. Write response is always set to OKAY. Write response is generated only when AXI4 ID is enabled for Memory Slave. Write response is not supported for Peripheral Slave configuration.
LogiCORE IP Block Memory Generator v6.1 Table 19: AXI4 Read Channel Interface Signals (Cont’d) Name Direction Description AXI4 Read Data Channel Interface Signals S_AXI_RID[m:0] Output Read ID Tag. This signal is the ID tag of the Read data group of signals. The RID value is generated by the slave and must match the ARID value of the Read transaction to which it is responding. Read ID tag is optional for Memory Slave configuration and is not supported for Peripheral Slave configuration.
LogiCORE IP Block Memory Generator v6.1 Table 20: AXI4-Lite Write Channel Interface Signals (Cont’d) Name Direction Description AXI4-Lite Write Data Channel Interface Signals S_AXI_WDATA[m-1:0] Input Write Data. For Memory Slave configurations, the Write data bus can be 32 or 64 bits wide. For Peripheral Slave configurations, the Write data bus can be 8, 16, 32 or 64 bits wide. S_AXI_WSTRB[m/8-1:0] Input Write Strobes. This signal indicates which byte lanes to update in memory.
LogiCORE IP Block Memory Generator v6.1 Table 21: AXI4-Lite Read Channel Interface Signals (Cont’d) Name S_AXI_ARVALID S_AXI_ARREADY Direction Input Output Description Read Address Valid. This signal indicates, when HIGH, that the Read address and control information is valid and will remain stable until the address acknowledge signal, ARREADY, is high. 1 = address and control information valid 0 = address and control information not valid Read Address Ready.
LogiCORE IP Block Memory Generator v6.1 • Native Block Memory Generator First Screen • Port Options Screen • Output Registers and Memory Initialization Screen • Reset Options Screen • Simulation Model Options and Information Screen In addition, all the screens share common tabs and buttons to provide information about the core and to navigate the Block Memory Generator GUI.
LogiCORE IP Block Memory Generator v6.1 • AXI4: Implements an AXI4 Interface Block Memory Generator Core. Native Block Memory Generator First Screen X-Ref Target - Figure 54 Figure 54: Block Memory Generator Main Screen Component Name The base name of the output files generated for the core. Names must begin with a letter and be composed of any of the following characters: a to z, 0 to 9, and “_”. Names can not be Verilog or VHDL reserved words. Memory Type Select the type of memory to be generated.
LogiCORE IP Block Memory Generator v6.1 • Built-In ECC. When targeting Kintex-7, Virtex-7, Virtex-6 and Virtex-5 devices, and when the selected ECC Type is BuiltIn_ECC, the built-in Hamming Error Correction is enabled for the Kintex-7, Virtex-7, Virtex-6, and Virtex-5 FPGA architecture. For the Kintex-7, Virtex-7, and Virtex-6 FPGA, the Use Error Injection Pins option is available for selection if the ECC option is selected. This option enables error injection pins.
LogiCORE IP Block Memory Generator v6.1 Write Enable When targeting Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A/3A DSP devices, select whether to use the byte-Write enable feature. Byte size is either 8-bits (no parity) or 9-bits (including parity). The data width of the memory will be multiples of the selected byte-size. Algorithm Select the algorithm used to implement the memory: • Minimum Area Algorithm: Generates a core using the least number of primitives.
LogiCORE IP Block Memory Generator v6.1 • • NO_CHANGE Enable Select the enable type: • Always enabled (no ENA pin available) • Use ENA pin Port B Options Screen • Memory Size Select the port B Write and Read widths from the drop-down list of valid choices. The Read depth is calculated automatically. • Operating Mode Specify the port B Write mode.
LogiCORE IP Block Memory Generator v6.1 Output Registers and Memory Initialization Screen X-Ref Target - Figure 56 Figure 56: Output Registers and Memory Initialization Screen Optional Output Registers Select the output register stages to include: 68 • Register Port [A|B] Output of Memory Primitives. Select to insert output register after the memory primitives for port A and port B separately.
LogiCORE IP Block Memory Generator v6.1 The MUX size displayed in the GUI can be used to determine the number of pipeline stages to use within the MUX. Select the appropriate number of pipeline stages for your design based on the device architecture. Memory Initialization Select whether to initialize the memory contents using a COE file, and whether to initialize the remaining memory contents with a default value.
LogiCORE IP Block Memory Generator v6.1 • Output Reset Value (Hex): Specify the reset value of the memory output latch and output registers. These values are with respect to the Read port widths. Reset Type The Reset Type option is available only for Spartan-6 devices and when either or both of Use RSTA Pin or Use RSTB Pin option are chosen. The user can set the reset type to either Synchronous or Asynchronous. For more information on this option, see Asynchronous Reset, page 41. 70 www.xilinx.
LogiCORE IP Block Memory Generator v6.1 Simulation Model Options and Information Screen X-Ref Target - Figure 58 Figure 58: Simulation Model Options and Information Screen DS512 March 1, 2011 Product Specification www.xilinx.
LogiCORE IP Block Memory Generator v6.1 Power Estimate Options X-Ref Target - Figure 59 Figure 59: Power Estimate Options Screen The Power Estimation tab on the left side of the GUI screen shown in Figure 59 provides a rough estimate of power consumption for the core based on the configured Read width, Write width, clock rate, Write rate and enable rate of each port. The power consumption calculation assumes a toggle rate 50%.
LogiCORE IP Block Memory Generator v6.1 Behavioral Simulation Model Options Select the type of warning messages generated by the behavioral simulation model. Select whether the model should assume synchronous clocks (Common Clock) for collision warnings. Information Section This section displays an informational summary of the selected core options. • Memory Type: Reports the selected memory type.
LogiCORE IP Block Memory Generator v6.1 • If the memory width is an integral multiple of the width of the widest available primitive for the chosen architecture, then the number of primitives used is calculated in the same way as the fixed primitive algorithm. The width and depth ratios are calculated using the width and depth of the widest primitive. For example, for a memory configuration of 2kx72, the width ratio is 2 and the depth ratio is 4 using the widest primitive of 512x36.
LogiCORE IP Block Memory Generator v6.1 Interface Type Selection Screen The main Block Memory Generator screen is used to define the component name and provides the Interface Options for the core. X-Ref Target - Figure 60Interface Options for the core. Figure 60: Interface Selection Screen of Block Memory Generator Component Name Base name of the output files generated for this core. The name must begin with a letter and be composed of the following characters: a to z, 0 to 9, and "_".
LogiCORE IP Block Memory Generator v6.1 AXI4 Interface Options X-Ref Target - Figure 61 Figure 61: AXI4 Interface Options AXI4 Interface Options • AXI4: Implements an AXI4 Block Memory Generator Core. • AXI4-Lite: Implements an AXI4-Lite Block Memory Generator Core.
LogiCORE IP Block Memory Generator v6.1 Block Memory Generator Resource Utilization and Performance Examples Native Block Memory Generator Resource Utilization and Performance Examples The following tables provide examples of actual resource utilization and performance for Native Block Memory Generator implementations. Each section highlights the effects of a specific feature on resource utilization and performance.
LogiCORE IP Block Memory Generator v6.1 Table 23: Single Primitive Examples - Virtex-5 FPGAs Memory Type True Dual-port RAM Options Width x Depth Resource Utilization Block RAMs 36K 16K 8K Shift Regs FFs LUTs (1) Performance (MHz) No Output Registers 36x512 1 0 0 0 0 0 300 9x2k 0 1 0 0 0 0 325 Embedded Output Registers 36x512 1 0 0 0 0 0 450 9x2k 0 1 0 0 0 0 450 1.
LogiCORE IP Block Memory Generator v6.1 In Virtex-6, Virtex-5, Virtex-4, and Spartan-6 architectures, the embedded block RAM may be utilized, reducing the FPGA fabric resources required to create the registers.
LogiCORE IP Block Memory Generator v6.1 1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
LogiCORE IP Block Memory Generator v6.1 2. Read port is 136x640; Write port is 17x5k. Algorithm The differences between the minimum area, low power and fixed primitive algorithms are discussed in detail in Selectable Memory Algorithm, page 4. Table 33 shows examples of the resource utilization and the performance difference between them for two selected configurations for Virtex-6 FPGA architectures.
LogiCORE IP Block Memory Generator v6.1 Table 35 shows examples of the resource utilization and the performance difference between them for two selected configurations for Virtex-4 FPGA architecture.
LogiCORE IP Block Memory Generator v6.1 AXI4 Block Memory Generator Resource Utilization and Performance Examples Table 37 through Table 40 show the resource utilization and performance data for a BMG core using the AXI4 interface. Benchmarks were taken using a design targeting a Virtex-6 FPGA in the -2 speed grade (XC6VCX75T-FF484-2) and a Spartan-6 FPGA in the -2 speed grade (XC6SLX150T-FGG484-2). Better performance may be possible with higher speed grades.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 www.xilinx.com/products/design_resources/power_central/index.htm XPE is a pre-implementation power estimation tool appropriate for estimating power requirements in the early stages of a design. For more accurate power consumption estimates and power analysis, the Xilinx Power Analyzer tool (XPA) available in ISE can be run on designs after place and route. Power data shown in the following tables was collected assuming a 50% toggle rate and 50% Write rate.
LogiCORE IP Block Memory Generator v6.1 • The Low Power algorithm disables the “Always Enabled” option for the Port A and Port B enable pins, and the user is forced to have these pins at the output (the “Use EN[A|B] Pin” option). These pins must not be permanently tied to ‘1’ if it is desired that power be conserved. Each port’s enable pin must be asserted high only when that port of the block RAM needs to be accessed. • Use of output registers improves performance, but also increases power consumption.
LogiCORE IP Block Memory Generator v6.1 should contain 256 32-bit wide entries. The first 128 entries initialize memory A, while the second 128 entries initialize memory B, as shown in Figure 62.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 Table 43: Native Interface SIM Parameters (Cont’d) SIM Parameter 50 51 C_RSTRAM_B C_HAS_INJECTERR 52 C_USE_SOFTECC 53 C_HAS_SOFTECC_INPUT_ REGS_A 54 C_HAS_SOFTECC_OUTPU T_REGS_B Type Integer Integer Integer Integer Integer Values Description ([0,1] : 1) Applicable for Kintex-7, Virtex-7, Virtex-6, Spartan-3A DSP, and Spartan-6 devices.
LogiCORE IP Block Memory Generator v6.1 Table 44: AXI4 Interface SIM Parameters (Cont’d) SIM Parameter 92 Type Values Description 4 C_INTERFACE_TYPE Integer 0: Native 1: AXI4 Determines the type of interface selected. 5 C_AXI_TYPE Integer 0: AXI4_Lite 1: AXI4_Full Determines the type of the AXI4 interface. 6 C_AXI_SLAVE_TYPE Integer 0: Memory Slave 1: Peripheral Slave Determines the type of the AXI4 Slave interface.
LogiCORE IP Block Memory Generator v6.1 Table 44: AXI4 Interface SIM Parameters (Cont’d) SIM Parameter Type Values Description 20 C_HAS_MEM_OUTPUT_REGS_A Integer 0 Determines whether port A has a register stage added at the output of the memory latch. 21 C_HAS_MEM_OUTPUT_REGS_B Integer 0 Determines whether port B has a register stage added at the output of the memory latch.
LogiCORE IP Block Memory Generator v6.1 Table 44: AXI4 Interface SIM Parameters (Cont’d) SIM Parameter Values Description 44 C_HAS_REGCEB Integer 0 Determines whether port B has an enable pin for its output register. 45 C_HAS_RSTB Integer 0 Determines whether port B has reset pin. 46 C_INITB_VAL String “…” Defines initialization/power-on value for port B output. 0, 1 Determines whether byte-Write feature is used on port B.
LogiCORE IP Block Memory Generator v6.1 Table 44: AXI4 Interface SIM Parameters (Cont’d) SIM Parameter 54 C_RSTRAM_B 55 C_HAS_INJECTERR 56 C_USE_SOFTECC C_HAS_SOFTECC_INPUT 57 _REGS_A C_HAS_SOFTECC_OUTPUT 58 _REGS_B 59 C_SIM_COLLISION_CHECK DS512 March 1, 2011 Product Specification Type Integer Integer Integer Integer Integer String Values Description 0 Applicable for Kintex-7, Virtex-7, Virtex-6, Spartan-3A DSP, and Spartan-6 devices.
LogiCORE IP Block Memory Generator v6.1 Output Register Configurations The Block Memory Generator core provides optional output registers that can be selected for port A and port B separately, and that may improve the performance of the core.
LogiCORE IP Block Memory Generator v6.1 For Kintex-7, Virtex-7, and Virtex-6, when only Register Port [A|B] Output of Memory Primitives and the corresponding Use RST[A|B] Pin are selected, the special reset behavior (option to reset the memory latch, in addition to the primitive output register) becomes available. For more information on this reset behavior, see Special Reset Behavior, page 39.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 Virtex-5 FPGA: Memory with Primitive Output Registers When Register Port [A|B] Output of Memory Primitives is selected, a memory core that registers the output of the block RAM primitives for the selected port(s) is generated. In Virtex-5 devices, these registers are always implemented using the output registers embedded in the Virtex-5 FPGA block RAM architecture.
LogiCORE IP Block Memory Generator v6.1 Virtex-4 FPGA: Memory with Primitive Output Registers without RST When Register Port [A|B] Output of Memory Primitives is selected and the corresponding Use RST [A|B] Pin (set/reset pin) is unselected, a memory core that registers the output of the block RAM primitives for the selected port(s) using the output registers embedded in Virtex-4 FPGA architecture is generated.
LogiCORE IP Block Memory Generator v6.1 Virtex-4 FPGA: Memory with Primitive Output Registers with RST If either Use RSTA Pin (set/reset pin) or Use RSTB Pin (set/reset pin) is selected from the Output Reset section of the Port Options screen(s), the Virtex-4 embedded block RAM registers cannot be used for the corresponding port(s). The primitive output registers are built from FPGA fabric, as shown in Figure 69.
LogiCORE IP Block Memory Generator v6.1 Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA: Memory with Core Output Registers When only Register Port [A|B] Output of Memory Core is selected, the Kintex-7/Virtex-6/Virtex6/Virtex-5/Virtex-4 device’s embedded registers are disabled for the selected ports in the generated core, as shown in Figure 70.
LogiCORE IP Block Memory Generator v6.1 Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA: Memory with No Output Registers If neither of the output registers is selected for ports A or B, output of the memory primitives is driven directly from the RAM primitive latches. In this configuration, as shown in Figure 71, there are no additional clock cycles of latency, but the clock-to-out delay for a Read operation can impact design performance.
LogiCORE IP Block Memory Generator v6.1 Spartan-6 or Spartan-3A DSP FPGA: Output Register Configurations To tailor register options for Spartan-6 or Spartan-3A DSP device configurations, two selections for port A and two selections for port B are provided on screen 3 of the CORE Generator GUI in the Optional Output Registers section. The embedded output registers for the corresponding port(s) are enabled when Register Port [A|B] Output of Memory Primitives is selected.
LogiCORE IP Block Memory Generator v6.1 Spartan-6 or Spartan-3A DSP FPGA: Memory with Primitive and Core Output Registers With both Register Port [A|B] Output of Memory Primitives and the corresponding Register Port [A|B] Output of Memory Core selected, a memory core is generated with both the embedded output registers and a register on the output of the core for the selected port(s), as shown in Figure 72. This configuration may improve performance when building a large memory construct.
LogiCORE IP Block Memory Generator v6.1 Spartan-6 or Spartan-3A DSP FPGA: Memory With Primitive Output Registers – Without RST Pin When Register Port [A|B] Output of Memory Primitives is selected, and the corresponding Use RST Pin (set/reset pin) is not selected, a memory core that registers the output of the block RAM primitives for the selected port using the output registers embedded in Spartan-6 and Spartan-3A DSP FPGA architectures is generated.
LogiCORE IP Block Memory Generator v6.1 Spartan-6 or Spartan-3A DSP FPGA: Memory with Primitive Output Registers and without Special Reset Behavior Option If Use RSTA Pin (set/reset pin) or Use RSTB Pin (set/reset pin) is selected, and the Reset Behavior option (resets the memory latch in addition to the primitive output register) is not selected, the embedded block RAM registers of the Spartan-6 or Spartan-3ADSP device cannot be used.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.
LogiCORE IP Block Memory Generator v6.1 Spartan-6 or Spartan-3A DSP FPGA: Memory with Core Output Registers When Register Port [A|B] Output of Memory Core is selected, the Spartan-6 or Spartan-3A DSP FPGA embedded registers are disabled in the generated core, as illustrated in Figure 76.
LogiCORE IP Block Memory Generator v6.1 Spartan-6 or Spartan-3A DSP FPGA: Memory with No Output Registers If no output registers are selected for port A or B, output of the memory primitive is driven directly from the RAM primitive latches. In this configuration, as shown in Figure 77, there are no additional clock cycles of latency, but the clock-to-out delay for a Read operation can impact design performance.
LogiCORE IP Block Memory Generator v6.1 Spartan-3 FPGA: Memory with Primitive and Core Output Registers With Register Port [A|B] Output of Memory Primitives and the corresponding Register Port [A|B] Output of Memory Core selected, a memory core is generated with registers on the outputs of the individual RAM primitives and on the core output, as displayed in Figure 78. Selecting this configuration may provide improved performance for building large memory constructs.
LogiCORE IP Block Memory Generator v6.1 Spartan-3 FPGA: Memory with Primitive Output Registers When Register Port [A|B] Output of Memory Primitives is selected, a core that only registers the output of the RAM primitives is generated. Note that the output of any multiplexing required to combine multiple primitives are not registered in this configuration, as shown in Figure 79.
LogiCORE IP Block Memory Generator v6.1 Spartan-3 FPGA: Memory with Core Output Registers Figure 80 illustrates a memory configured with Register Port [A|B] Output of Memory Core selected.
LogiCORE IP Block Memory Generator v6.1 Spartan-3 FPGA: Memory with No Output Registers When no output register options are selected for either port A or port B, the output of the memory primitive is driven directly from the memory latches. In this configuration, there are no additional clock cycles of latency, but the clock-to-out delay for a Read operation can impact design performance. See Figure 81.
LogiCORE IP Block Memory Generator v6.1 Support Xilinx provides technical support for this LogiCORE product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
LogiCORE IP Block Memory Generator v6.1 Notice of Disclaimer Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice.
