User guide

DS512 March 1, 2011 www.xilinx.com 101
Product Specification
LogiCORE IP Block Memory Generator v6.1
Virtex-4 FPGA: Memory with Primitive Output Registers without RST
When Register Port [A|B] Output of Memory Primitives is selected and the corresponding Use RST
[A|B] Pin (set/reset pin) is unselected, a memory core that registers the output of the block RAM
primitives for the selected port(s) using the output registers embedded in Virtex-4 FPGA architecture is
generated. The output of any multiplexing that may be required to combine multiple primitives is not
registered in this configuration, as shown in Figure 68.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core
 Use RSTA Pin (set/reset pin)  Use RSTB Pin (set/reset pin)
X-Ref Target - Figure 68
Figure 68: Virtex-4 Block Memory Generated with only Register Port [A | B]
Output of Memory Primitives Enabled
Block Memory Generator Core
Latches
Latches
FALSE
Block RAM Primitives
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
EN
Use REGCE Pin
REGCE
CLK
TRUE
MUX
D
Latches
CE
DQ