User guide

LogiCORE IP Block Memory Generator v6.1
104 www.xilinx.com DS512 March 1, 2011
Product Specification
Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA: Memory with No Output Regis-
ters
If neither of the output registers is selected for ports A or B, output of the memory primitives is driven
directly from the RAM primitive latches. In this configuration, as shown in Figure 71, there are no
additional clock cycles of latency, but the clock-to-out delay for a Read operation can impact design
performance.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core
X-Ref Target - Figure 71
Figure 71: Kintex-7, Virtex-7, Virtex-6, Virtex-5 or Virtex-4 Block Memory Generated with No
Output Registers Enabled
Block Memory Generator Core
Latches
Latches
Block RAM Primitives
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
EN
MUX
CLK
RST
DOUT