User guide

DS512 March 1, 2011 www.xilinx.com 107
Product Specification
LogiCORE IP Block Memory Generator v6.1
Spartan-6 or Spartan-3A DSP FPGA: Memory With Primitive Output Registers – With-
out RST Pin
When Register Port [A|B] Output of Memory Primitives is selected, and the corresponding Use RST
Pin (set/reset pin) is not selected
, a memory core that registers the output of the block RAM primitives
for the selected port using the output registers embedded in Spartan-6 and Spartan-3A DSP FPGA
architectures is generated. The output of any multiplexing that may be required to combine multiple
primitives is not registered in this configuration (Figure 73).
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core

Use RSTA Pin (set/reset pin)  Use RSTB Pin (set/reset pin)
X-Ref Target - Figure 73
Figure 73: Spartan-6 or Spartan-3A DSP Block Memory Generated with Register Port [A|B]
Output of Memory Primitives Enabled (No RST)
Block Memory Generator Core
Latches
Latches
FALSE
Block RAM Primitives
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
EN
Use REGCE Pin
REGCE
CLK
TRUE
MUX
DOUT
Latches
CE
DQ