User guide

LogiCORE IP Block Memory Generator v6.1
108 www.xilinx.com DS512 March 1, 2011
Product Specification
Spartan-6 or Spartan-3A DSP FPGA: Memory with Primitive Output Registers and with-
out Special Reset Behavior Option
If Use RSTA Pin (set/reset pin) or Use RSTB Pin (set/reset pin) is selected, and the Reset Behavior option
(resets the memory latch in addition to the primitive output register) is not selected, the embedded
block RAM registers of the Spartan-6 or Spartan-3ADSP device cannot be used.The primitive output
registers are built from FPGA fabric, as illustrated in Figure 74.
Note:
This behavior is the same as that of Spartan-3, Spartan-3A, Virtex-5 and Virtex-4 devices.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core

Use RSTA Pin (set/reset pin)  Use RSTB Pin (set/reset pin)
 Reset Memory Latch  Reset Memory Latch
X-Ref Target - Figure 74
Figure 74: Spartan-6 or Spartan-3A DSP Block Memory Generated with Register Port [A|B]
Output of Memory Primitives, Use RST[A|B] Pin Options (With RST), without Special Reset
Behavior
Block Memory Generator Core
Latches
Latches
FALSE
Block RAM Primitives
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
EN
Use REGCE Pin
REGCE
CLK
RST
R* : The reset (R) of the flop is gated by CE
TRUE
Primitive
Output Registers
CE
R*
DQ
CE
R*
DQ
CE
R*
DQ
MUX
DOUT