User guide

DS512 March 1, 2011 www.xilinx.com 109
Product Specification
LogiCORE IP Block Memory Generator v6.1
Spartan-6 or Spartan-3A DSP FPGA: Memory with Primitive Output Registers and with
Special Reset Behavior Option (Embedded Registers)
When Register Port [A|B] Output of Memory Primitives, Use RSTA Pin (set/reset pin) or Use RSTB Pin
(set/reset pin), and
the special reset behavior (resets the memory latch in addition to the primitive
output register) are selected, the Spartan-6 or Spartan-3A DSP embedded registers are enabled for the
selected port in the generated core, as displayed in Figure 75.
If the special reset behavior option is selected, the Spartan-6 or Spartan-3A DSP FPGA’s embedded
output registers are used, but the reset behavior of the core changes as described in Special Reset
Behavior, page 39. The functional differences between this and other implementations are that the
RST[A|B] input resets both the embedded output registers and the block RAM output latches.
For Spartan-3ADSP devices, if EN and REGCE are held high, the output value is set to the reset value for
two clock cycles following a reset. In addition, the synchronous reset for both the latches and the
embedded output registers are gated by the EN input to the core, independent of the state of REGCE, as
shown in Figure 75. This differs from all other configurations of the Block Memory Generator where
RST is typically gated by REGCE.
For Spartan-6 devices, if REGCE is held high, the output value is set to the reset value for two clock
cycles following a reset. Unlike Spartan-3A DSP devices, and similar to other architectures, reset is
gated by REGCE.