User guide

DS512 March 1, 2011 www.xilinx.com 111
Product Specification
LogiCORE IP Block Memory Generator v6.1
Spartan-6 or Spartan-3A DSP FPGA: Memory with Core Output Registers
When Register Port [A|B] Output of Memory Core is selected, the Spartan-6 or Spartan-3A DSP FPGA
embedded registers are disabled in the generated core, as illustrated in Figure 76.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core

Use RSTA Pin (set/reset pin)  Use RSTB Pin (set/reset pin)
X-Ref Target - Figure 76
Figure 76: Spartan-6 or Spartan-3A DSP Block Memory Generated with Register Port [A|B]
Output of Memory Core Enabled
Block Memory Generator Core
Core
Output
Registers
Latches
Latches
FALSE
Block RAM Primitives
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
EN
Use REGCE Pin
REGCE
MUX
CLK
RST
DOUT
CE
R*
DQ
R* : The reset (R) of the flop is gated by CE
TRUE