User guide

LogiCORE IP Block Memory Generator v6.1
112 www.xilinx.com DS512 March 1, 2011
Product Specification
Spartan-6 or Spartan-3A DSP FPGA: Memory with No Output Registers
If no output registers are selected for port A or B, output of the memory primitive is driven directly
from the RAM primitive latches. In this configuration, as shown in Figure 77, there are no additional
clock cycles of latency, but the clock-to-out delay for a Read operation can impact design performance.
Spartan-3 FPGA: Output Register Configurations
To tailor register options for Spartan-3 FPGA architectures, two selections for port A and two selections
for port B are provided in the CORE Generator GUI on screen 4 in the Optional Output Registers
section. For implementing registers on the outputs of the individual block RAM primitives, Register
Output of Memory Primitives is selected. In the same way, registering the output of the core is enabled
by selecting Register Port [A|B] Output of Memory Core. Four implementations are available for each
port. Figure 78, Figure 79, Figure 80, and Figure 81 illustrate the Spartan-3 FPGA output register
configurations.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core
X-Ref Target - Figure 77
Figure 77: Spartan-6 or Spartan-3A DSP Block Memory Generated with No Output Port
Registers Enabled
Block Memory Generator Core
Latches
Latches
Block RAM Primitives
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
N/A
Latches
EN
MUX
CLK
RST
DOUT