User guide

DS512 March 1, 2011 www.xilinx.com 113

Product Specification

LogiCORE IP Block Memory Generator v6.1

Spartan-3 FPGA: Memory with Primitive and Core Output Registers

With Register Port [A|B] Output of Memory Primitives and the corresponding Register Port [A|B]

Output of Memory Core selected, a memory core is generated with registers on the outputs of the

individual RAM primitives and on the core output, as displayed in Figure 78. Selecting this

configuration may provide improved performance for building large memory constructs.

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

X-Ref Target - Figure 78

Figure 78: Spartan-3 Block Memory Generated with Register Port [A|B] Output of Memory

Primitives and Register Port [A|B] Output of Memory Core Options Enabled

Block Memory Generator Core

Latches

REGCE

MUX

Block RAM Primitives

Block RAM

CLK

RST

DOUT

S* : The synchronous reset (S) of the flop is gated by CE

Block RAM

Latches

FALSE

Use REGCE Pin

TRUE

Primitive

Output

Registers

Core

Output

Registers