User guide

DS512 March 1, 2011 www.xilinx.com 115
Product Specification
LogiCORE IP Block Memory Generator v6.1
Spartan-3 FPGA: Memory with Core Output Registers
Figure 80 illustrates a memory configured with Register Port [A|B] Output of Memory Core selected.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core
X-Ref Target - Figure 80
Figure 80: Spartan-3 Block Memory Generated with Register Port [A|B] Output of Memory Core
Enabled
Block Memory Generator Core
Core
Output
Registers
Latches
Latches
EN
REGCE
MUX
Block RAM Primitives
Block RAM
CLK
RST
DOUT
S* : The synchronous reset (S) of the flop is gated by CE
Block RAM
Block RAM
Latches
CE
S*
DQ
FALSE
Use REGCE Pin
TRUE