User guide

LogiCORE IP Block Memory Generator v6.1

116 www.xilinx.com DS512 March 1, 2011

Product Specification

Spartan-3 FPGA: Memory with No Output Registers

When no output register options are selected for either port A or port B, the output of the memory

primitive is driven directly from the memory latches. In this configuration, there are no additional

clock cycles of latency, but the clock-to-out delay for a Read operation can impact design performance.

See Figure 81.

Block Memory Generator Verification

The Block Memory Generator core and the simulation models delivered with it are rigorously verified

using advanced verification techniques, including a constrained random configuration generator and a

cycle-accurate bus functional model.

References

See the following references for more information. Xilinx documentation can be found at

www.xilinx.com/support/documentation/index.htm

1. AXI4 AMBA® AXI Protocol Version: 2.0 Specification

2. UG761, Xilinx AXI Reference Guide

Port A or Port B

 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives

 Register Port A Output of Memory Core  Register Port B Output of Memory Core

X-Ref Target - Figure 81

Figure 81: Spartan-3 Block Memory Generated with No Output Registers Enabled

Block Memory Generator Core

Latches

MUX

Block RAM Primitives

Block RAM

CLK

RST

DOUT

Block RAM

Latches