User guide

LogiCORE IP Block Memory Generator v6.1

28 www.xilinx.com DS512 March 1, 2011

Product Specification

Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 Read-to-Write Aspect Ratios

When implementing RAMs targeting Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs, the

Block Memory Generator allows Read and Write aspect ratios on either port. On each port A and port

B, the Read to Write data width ratio of that port can be 1:32, 1:16, 1:8, 1:4, 1:2, 1:1, 2:1, 4:1, 8:1, 16:1, or

32:1.

Because the Read and Write interfaces of each port can differ, it is possible for all four data buses (DINA,

DOUTA, DINB, and DOUTB) of True Dual-port RAMs to have a different width. For Single-port RAMs,

DINA and DOUTA widths can be independent. The maximum ratio between any two data buses is 32:1.

The widest data bus can be no larger than 1152 bits.

If the Read and Write data widths on a port are different, the memory depth is different with respect to

Read and Write accesses. For example, if the Read interface of port A is twice as wide as the Write

interface, then it is also half as deep. The ratio of the widths is always the inverse of the ratio of the

depths. Because a single address bus is used for both the Write and Read interface of a port, the address

bus must be large enough to address the deeper of the two depths. For the shallower interface, the least

significant bits of the address bus are ignored. The data words are arranged in little-endian format, as

illustrated in Figure 30.

Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 Read-to-Write Aspect Ratio Example

Consider a True Dual-port RAM of 64x512, which is the port A Write width and depth. Table 7 defines

the four data-port widths and their respective depths for this example.

The

ADDRA width is determined by the larger of the A port depths (2048). For this reason, ADDRA is 11

bits wide. On port A, Read operations utilize the entire

ADDRA bus, while Write operations ignore the

least significant 2 bits.

In the same way, the

ADDRB width is determined by the larger of the B port depths (1024). For this

reason,

ADDRB is 10 bits wide. On port B, Read operations utilize the entire ADDRB bus, while Write

operations ignore the least significant 3 bits.

The memory map in Figure 30 shows how port B Write words are related to port A Write words, in a

little-endian arrangement. Note that AW

is the Write data word at address n with respect to port A,

while BW

is the Write data word at address n with respect to port B.

Table 7: Read-to-Write Aspect Ratio Example Ports

Interface Data Width Memory Depth

Port A Write 64 512

Port A Read 16 2048

Port B Write 256 128

Port B Read 32 1024

X-Ref Target - Figure 30

Figure 30: Read-to-Write Aspect Ratio Example Memory Map

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