User guide

DS512 March 1, 2011 www.xilinx.com 33

Product Specification

LogiCORE IP Block Memory Generator v6.1

Figure 34 shows a memory configuration with registers at the output of the memory primitives and at

the output of the core for one of the ports.

X-Ref Target - Figure 34

Figure 34: Spartan-3 Block Memory: Register Port [A|B] Outputs of Memory Primitives

and Memory Core Options Enabled

Block Memory Generator Core

Latches

REGCE

MUX

Block RAM Primitives

Block RAM

CLK

RST

DOUT

S* : The synchronous reset (S) of the flop is gated by CE

Block RAM

Latches

FALSE

Use REGCE Pin

TRUE

Primitive

Output

Registers

Core

Output

Registers