User guide

LogiCORE IP Block Memory Generator v6.1
36 www.xilinx.com DS512 March 1, 2011
Product Specification
Optional Register Clock Enable Pins
The optional output registers are enabled by the EN signal by default. However, when the Use
REGCEA/REGCEB Pin option is selected, the output register stage of the corresponding port is
controlled by the REGCEA/REGCEB pins; the data output from the core can be controlled
independent of the flow of data through the rest of the core. When using the
REGCE pin, the last output
register operates independent of the
EN signal.
X-Ref Target - Figure 36
Figure 36: Memory Configuration with 8:1 MUX and Two Pipeline Stages within the MUX
D Q
D Q
D Q
D Q
2:1
2:1
2:1
2:1
2:1
2:1
2:1
D Q
>
D Q
>
D Q
CE
>
R*
DOUT
block RAMs
Pipeline Stage 1
Pipeline Stage 2
8:1 MUX
(After pipelining)
Use REGCE Pin
REGCE
RST
CLK
EN
Core
Output
Registers
False
True
R*: Reset (R) of the flop is gated by CE
vvvv