User guide

DS512 March 1, 2011 www.xilinx.com 45

Product Specification

LogiCORE IP Block Memory Generator v6.1

Figure 46 illustrates a typical Write and Read operation for a Kintex-7, Virtex-7, Virtex-6, and Virtex-5

FPGA Block Memory Generator core in Simple Dual-port RAM mode with BuiltIn_ECC enabled, and

no additional output registers.

Error Injection

For Virtex-5, the Block Memory Generator core does not support the insertion of errors for correction

by BuiltIn_ECC in simulation. For this reason, the simulated functionality of ECC is identical to non-

ECC behavior with the SBITERR and DBITERR outputs always disabled.

Kintex-7, Virtex-7, and Virtex-6 devices, however, support error injection through two new optional

pins: INJECTSBITERR and INJECTDBITERR. Users can use these optional error injection pins as

debug pins to inject single or double-bit errors into specific locations during Write operations. The user

can then check the assertion of the SBITERR and DBITERR signals at the output of those addresses. The

user has the option to have no error injection pins, or to have only one or both of the error injection pins.

The RDADDRECC output port indicates the address at which a SBITERR or DBITERR has occurred. The

RDADDRECC port, the two error injection ports, and the two error output ports are optional and become

available only when the BuiltIn_ECC option is chosen. If the BuiltIn_ECC feature is not selected by the

user, the primitive's INJECTSBITERR and INJECTDBITERR ports are internally driven to '0', and the

primitive's outputs SBITERR, DBITERR, and RDADDRECC are not connected externally.

X-Ref Target - Figure 46

Figure 46: Read and Write Operation with BuiltIn_ECC in

Kintex-7, Virtex-7, Virtex-6, and Virtex-5 FPGAs

WEA

DINA

CLKA, CLKB

ADDRA

ADDRB

DOUTB

DBITERR

SBITERR

ENB

ENA

1111 2222

1100