User guide

DS512 March 1, 2011 www.xilinx.com 47
Product Specification
LogiCORE IP Block Memory Generator v6.1
• Single-bit errors are corrected
• Double-bit errors are detected
• Supports Simple Dual-port RAM memory type
• Supports optional Input and/or Output Registering stages
• Supported Block Memory Generator features include:
• Minimum Area, Fixed Primitive and Low Power Algorithms
• Mux Pipelining Stages
• Embedded Primitive Registers
• Core Output Registers
• Optional Enable Inputs
• Fully parameterized implementation enables optimization of resources
Details
Each Write operation generates between 4 and 8 protection bits for 1 to 64 bits of data, which are stored
with the data in memory. These bits are used during each Read operation to correct any single-bit error,
or to detect (but not correct) any double-bit error.
The two status outputs (SBITERR and DBITERR) indicate the three possible Read results: no error,
single error corrected, and double error detected. For single-bit errors, the Read operation does not
correct the error in the memory array; it only presents corrected data on DOUT.
When using Soft ECC, the Block Memory Generator can construct the memory from the available
primitives in Kintex-7, Virtex-7, Virtex-6, and Spartan-6 FPGA architectures. The Soft ECC feature is
implemented as an overlay on top of the Block Memory Generator core. This allows users to select
algorithm options and registering options in the core. When Soft ECC is selected, limited core options
include:
• Byte-Write enable is not available
• All port widths must be identical
• Use RST[A|B] Pin and the Output Reset Value options are not available
• Memory Initialization is not supported
The Soft ECC implementation is optimized to generate the core for different data widths, as shown in
Table 10. For the selected data width, the number of check bits appended is shown in Table 11. The
operation of appending the additional check bits for the given data width is done within the Block
Memory Generator core and is transparent to the user.
Table 10: Soft ECC Data width Support
Spartan-6 Kintex-7 Virtex-5 Virtex-6 Virtex-7
Block RAM
mode
SDP Mode SDP Mode No SDP Mode SDP Mode
Supported Data
Widths
64 bits 64 bits n/a 64 bits 64 bits
Bit Error
Insertion
Support
Yes Yes n/a Yes Yes