User guide
LogiCORE IP Block Memory Generator v6.1
48 www.xilinx.com DS512 March 1, 2011
Product Specification
.
Figure 48 illustrates the implementation of Soft ECC logic for the Block Memory Generator core. The
implementation shown in Figure 48 is for 64 bits of data; the implementation is parameterized for other
data widths.
The optional input and output registering stages can be enabled by setting the values of parameters
register_porta_input_of_softecc and register_portb_output_of_softecc appropriately. These registers
improve the performance of the Soft ECC logic. By default, the input and output registering stages are
disabled.
With Soft ECC, both Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices support error injection through
two new optional pins: INJECTSBITERR and INJECTDBITERR. The error injection operation is
performed on both data bits and added check bits. Users can use these optional error injection pins as
debug pins to inject single or double-bit errors into specific locations during Write operations. Then, the
user can check the assertion of the SBITERR and DBITERR signals at the output of those addresses. The
user may select no error injection pins, one error injection pin or both.
The RDADDRECC output port indicates the address at which a single or double-bit error has occurred.
The RDADDRECC port, the two error injection ports, and the two error output ports are optional and
become available only when the Soft ECC option is chosen. If the Soft ECC feature is not selected, the
outputs SBITERR, DBITERR, and RDADDRECC are not connected externally.
Table 11: Memory Width Calculation for Selected User Data Width
User Input Data Width Added Check Bits Total Memory Width in Bits
1-4 4 5-8
5-11 5 10-16
12-26 6 18-32
27-57 7 34-64
58-64 8 66-72
X-Ref Target - Figure 48
Figure 48: Block Memory Generator with SoftECC
Block Memory Generator With Soft ECC
FF
FF
Block Memory
Generator
FF
FF
X
0000…….0011
ROR
0000…….0001
0000…….0000
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CB8
Data [63:0]
Mask Generation
Error Reporting
Data
[63:0]
Check
Bits
[7:0]
Check
Bits
[7:0]
DINA
[71:0]
ADDRA
WEA
ENA
ADDRB
WEB
REGCEB
ADDRB
WEB
REGCEB
SBITERR
DBITERR
RDADDRECC
INJECTSBITERR
INJECTDBITERR
DINA [63:0]
ADDRA
WEA
ENA
DINA [63:0]
DOUTB [63:0]
Single Bit
Error Correction
DOUTB
[71:0]
FF
Optional Registering Stages
X
XORing Logic
FF
X
X
X
X
X
X
X
X
X
X
X
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT