User guide

DS512 March 1, 2011 www.xilinx.com 53
Product Specification
LogiCORE IP Block Memory Generator v6.1
Figure 52 shows the assertion of the SBITERR and DBITERR output signals when errors are injected
through the error injection pins during a Write operation.
When the INJECTSBITERR and INJECTDBITERR inputs are asserted together at the same time for the
same address during a Write operation (address 3 in Figure 52 ), then the INJECTDBITERR input takes
precedence. Only the DBITERR output is asserted for that address during a Read operation. The data
output for this address is not corrected.
X-Ref Target - Figure 52
Figure 52: Assertion of SBITERR and DBITERR Signals
CLK
EN
NO
OPERATION
WRITE
READ
WE
1
ADDR
0 2 3 1 2 3 4
INJECTSBITERR
INJECTDBITERR
A
DIN
0 B C D E F 9
DOUT
0 A B C A Bx Cx
SBITERR
DBITERR
WRITE WRITE
READ READ READ
SBITERR
Corrected
Data
DBITERR
Incorrect
Data