User guide

DS512 March 1, 2011 www.xilinx.com 55
Product Specification
LogiCORE IP Block Memory Generator v6.1
Lower Data Widths in Kintex-7, Virtex-7, and Virtex-6 SDP Configurations
The Kintex-7, Virtex-7, and Virtex-6 FPGA architectures with the new SDP primitives support lower
data widths than the Virtex-5 FPGAs. In Virtex-5 devices, the RAMB18SDP primitive could only
support a symmetric configuration with port widths of 36, and the RAMB36SDP primitive could only
support a symmetric configuration with port widths of 72. For Kintex-7, Virtex-7, and Virtex-6 devices,
new width combinations are possible for Port A and Port B, as shown in Table 14.
Simulation Models
The Block Memory Generator core provides two types of functional simulation models:
• Behavioral Simulation Models (VHDL and Verilog)
• Structural/UniSim based Simulation Models (VHDL and Verilog)
The behavioral simulation models provide a simplified model of the core while the structural
simulation models (UniSim) are an accurate modeling of the internal structure of the core. The
behavioral simulation models are written purely in RTL and simulate faster than the structural
simulation models and are ideal for functional debugging. Moreover, the memory is modeled in a two-
dimensional array, making it easier to probe contents of the memory.
The structural simulation model uses primitive instantiations to model the behavior of the core more
precisely. Use the structural simulation model to accurately model memory collision behavior and 'x'
output generation. Note that simulation time is longer and debugging may be more difficult. The
Simulation Files options in the CORE Generator Project Options determine the type of functional
Table 14: Data Widths Supported by Kintex-7, Virtex-7, and Virtex-6 Device SDP Primitives
(1)
Primitive Read Port Width Write Port Width Read Port Width Write Port Width
RAMB18 SDP
Primitive
x1 x32 x32 x1
x2 x32 x32 x2
x4 x32 x32 x4
x9 x36 x36 x9
x18 x36 x36 x18
x36 x36 - -
RAMB36 SDP
Primitive
x1 x64 x64 x1
x2 x64 x64 x2
x4 x64 x64 x4
x9 x72 x72 x9
x18 x72 x72 x18
x36 x72 x72 x36
x72 x72 - -
Notes:
1. Refer to Additional Memory Collision Restrictions: Address Space Overlap, page 32.