User guide

LogiCORE IP Block Memory Generator v6.1
56 www.xilinx.com DS512 March 1, 2011
Product Specification
simulation models generated. Table 15 defines the differences between the two functional simulation
models.
Signal Lists
Native Block Memory Generator Signal List
Table 16 provides a description of the Block Memory Generator core signals. The widths of the data
ports (
DINA, DOUTA, DINB, and DOUTB) are selected by the user in the CORE Generator GUI. The
address port (
ADDRA and ADDRB) widths are determined by the memory depth with respect to each
port, as selected by the user in the GUI. The Write enable ports (
WEA and WEB) are busses of width 1
when byte-writes are disabled. When byte-writes are enabled,
WEA and WEB widths depend on the
byte size and Write data widths selected in the GUI.
Table 15: Differences between Simulation Models
Behavioral Models Structural Models (Unisim)
When core output is undefined Never generates ‘X’ Generates ‘X’ to match core
Out-of-range address access
Optionally flags a warning
message
Generates ‘X’
Collision behavior
Does not generate ‘X’ on output,
and flags a warning message
Generates ‘X’ to match core
Byte-Write collision behavior Flags all byte-Write collisions
Does not flag collisions if byte-
writes do not overlap
Table 16: Core Signal Pinout
Name Direction Description
CLKA Input
Port A Clock: Port A operations are synchronous to this clock. For
synchronous operation, this must be driven by the same signal as CLKB.
ADDRA Input
Port A Address: Addresses the memory space for port A Read and Write
operations. Available in all configurations.
DINA Input
Port A Data Input: Data input to be written into the memory via port A.
Available in all RAM configurations.
DOUTA Output
Port A Data Output: Data output from Read operations via port A. Available
in all configurations except Simple Dual-port RAM.
ENA Input
Port A Clock Enable: Enables Read, Write, and reset operations via port A.
Optional in all configurations.
WEA Input
Port A Write Enable: Enables Write operations via port A. Available in all
RAM configurations.
RSTA Input
Port A Set/Reset: Resets the Port A memory output latch or output register.
Optional in all configurations.
REGCEA Input
Port A Register Enable: Enables the last output register of port A. Optional
in all configurations with port A output registers.
CLKB Input
Port B Clock: Port B operations are synchronous to this clock. Available in
dual-port configurations. For synchronous operation, this must be driven by
the same signal as CLKA.
ADDRB Input
Port B address: Addresses the memory space for port B Read and Write
operations. Available in dual-port configurations.
DINB Input
Port B Data Input: Data input to be written into the memory via port B.
Available in True Dual-port RAM configurations.