User guide

LogiCORE IP Block Memory Generator v6.1
58 www.xilinx.com DS512 March 1, 2011
Product Specification
S_AXI_AWLEN[7:0] Input
Burst Length. The burst length gives the exact number of transfers in a
burst. This information determines the number of data transfers
associated with the address.
S_AXI_AWSIZE[2:0] Input
Burst Size. This signal indicates the size of each transfer in the burst. Byte
lane strobes indicate exactly which byte lanes to update.
Burst size should always be less than or equal to the width of the Write
Data.
Burst Size input is not supported for Peripheral Slave configuration.
S_AXI_AWBURST[1:0] Input
Burst Type. The burst type, coupled with the size information, details how
the address for each transfer within the burst is calculated.
Burst type for Memory Slave configuration could be either incremental or
wrap.
Burst type input is not supported for Peripheral Slave configuration, Burst
type for Peripheral Slave is always internally set to incremental.
S_AXI_AWVALID Input
Write Address Valid. This signal indicates that valid Write address and
control information are available:
• 1 = address and control information available.
• 0 = address and control information not available. The address and
control information remain stable until the address acknowledge signal,
AWREADY, goes HIGH.
S_AXI_AWREADY Output
Write Address Ready. This signal indicates that the slave is ready to
accept an address and associated control signals:
• 1 = Slave ready
• 0 = Slave not ready
AXI4 Write Data Channel Interface Signals
S_AXI_WDATA[m-1:0] Input
Write Data. For Memory Slave configurations, the Write data bus can be
32, 64, 128, or 256 bits wide. For Peripheral Slave configurations, the
Write data bus can be 8, 16, 32, 64, 128, or 256 bits wide.
S_AXI_WSTRB[m/8-1:0] Input
Write Strobes. This signal indicates which byte lanes to update in
memory. There is one Write strobe for each eight bits of the Write data bus.
Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)].
S_AXI_WLAST Input Write Last. This signal indicates the last transfer in a Write burst.
S_AXI_WVALID Input
Write Valid. This signal indicates that valid Write data and strobes are
available:
• 1 = Write data and strobes available
• 0 = Write data and strobes not available
S_AXI_WREADY Output
Write Ready. This signal indicates that the slave can accept the Write
data:
• 1 = slave ready
• 0 = slave not ready
AXI4 Write Response Channel Interface Signals
S_AXI_BID[m:0] Output
Response ID. The identification tag of the Write response. The BID value
must match the AWID value of the Write transaction to which the slave is
responding.
Response ID is optional for Memory Slave configuration and is not
supported for Peripheral Slave configuration.
Response ID can be 1 to 16 bits wide.
Table 18: AXI4 Write Channel Interface Signals (Cont’d)
Name Direction Description