User guide

DS512 March 1, 2011 www.xilinx.com 59
Product Specification
LogiCORE IP Block Memory Generator v6.1
S_AXI_BRESP[1:0] Output
Write Response. This signal indicates the status of the Write transaction.
The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
Write response is always set to OKAY.
Write response is generated only when AXI4 ID is enabled for Memory
Slave. Write response is not supported for Peripheral Slave configuration.
S_AXI_BVALID Output
Write Response Valid. This signal indicates that a valid Write response
is available:
• 1 = Write response available
• 0 = Write response not available
S_AXI_BREADY Input
Response Ready. This signal indicates that the master can accept the
response information.
• 1 = Master ready
• 0 = Master not ready
Table 19: AXI4 Read Channel Interface Signals
Name Direction Description
AXI4 Read Address Channel Interface Signals
S_AXI_ARID[m:0] Input
Read Address ID. This signal is the identification tag for the Read address
group of signals.
Read address ID is optional for Memory Slave configuration and is not
supported for Peripheral Slave configuration.
Read address ID can be 1 to 16 bits wide.
S_AXI_ARADDR[31:0] Input
Read Address. The Read address bus gives the initial address of a Read
burst transaction.
Only the start address of the burst is provided and the control signals that
are issued alongside the address detail how the address is calculated for the
remaining transfers in the burst.
S_AXI_ARLEN[7:0] Input
Burst Length. The burst length gives the exact number of transfers in a
burst. This information determines the number of data transfers associated
with the address.
S_AXI_ARSIZE[2:0] Input
Burst Size. This signal indicates the size of each transfer in the burst.
Burst size should always be less than or equal to the width of the Read Data.
Burst Size input is not supported for Peripheral Slave configuration.
S_AXI_ARBURST[1:0] Input
Burst Type. The burst type, coupled with the size information, details how
the address for each transfer within the burst is calculated.
Burst type for Memory Slave configuration could be either incremental or
wrap.
Burst type input is not supported for Peripheral Slave configuration, Burst
type for Peripheral Slave is always internally set to incremental.
S_AXI_ARVALID Input
Read Address Valid. This signal indicates, when HIGH, that the Read
address and control information is valid and will remain stable until the
address acknowledge signal, ARREADY, is high.
• 1 = address and control information valid
• 0 = address and control information not valid
S_AXI_ARREADY Output
Read Address Ready. This signal indicates that the slave is ready to accept
an address and associated control signals:
• 1 = slave ready
• 0 = slave not ready
Table 18: AXI4 Write Channel Interface Signals (Cont’d)
Name Direction Description