User guide

LogiCORE IP Block Memory Generator v6.1
60 www.xilinx.com DS512 March 1, 2011
Product Specification
AXI4-Lite Interface Signals
AXI4 Read Data Channel Interface Signals
S_AXI_RID[m:0] Output
Read ID Tag. This signal is the ID tag of the Read data group of signals. The
RID value is generated by the slave and must match the ARID value of the
Read transaction to which it is responding.
Read ID tag is optional for Memory Slave configuration and is not supported
for Peripheral Slave configuration.
Read ID can be 1 to 16 bits wide.
S_AXI_RDATA[m-1:0] Output
Read Data. For Memory Slave configurations, the Read data bus can be 32,
64, 128, or 256 bits wide. For Peripheral Slave configurations, the Read data
bus can be 8, 16, 32, 64, 128, or 256 bits wide.
S_AXI_RRESP[1:0] Output
Read Response. This signal indicates the status of the Read transfer. The
allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
Read response is always set to OKAY.
Read response is generated only when AXI4 ID is enabled for Memory
Slave. Read response is not supported for Peripheral Slave configuration.
S_AXI_RLAST Output Read Last. This signal indicates the last transfer in a Read burst.
S_AXI_RVALID Output
Read Valid. This signal indicates that the required Read data is available
and the Read transfer can complete:
• 1 = Read data available
• 0 = Read data not available
S_AXI_RREADY Input
Read Ready. This signal indicates that the master can accept the Read data
and response information:
• 1= Master ready
• 0 = Master not ready
Table 20: AXI4-Lite Write Channel Interface Signals
Name Direction Description
AXI4-Lite Write Address Channel Interface Signals
S_AXI_AWADDR[31:0] Input
Write Address. The Write address bus gives the address of the first
transfer in a Write burst transaction. The associated control signals are
used to determine the addresses of the remaining transfers in the burst.
S_AXI_AWVALID Input
Write Address Valid. This signal indicates that valid Write address and
control information are available:
• 1 = address and control information available
• 0 = address and control information not available.
The address and control information remain stable until the address
acknowledge signal, AWREADY, goes HIGH
S_AXI_AWREADY Output
Write Address Ready. This signal indicates that the slave is ready to
accept an address and associated control signals:
• 1 = slave ready
• 0 = slave not ready
S_AXI_AWID[m:0] Input
Write Address ID. This signal is the identification tag for the Write address
group of signals
Write address ID is optional for Memory Slave configuration and is not
supported for Peripheral Slave configuration.
Write address ID can be 1 to 16 bits wide.
Table 19: AXI4 Read Channel Interface Signals (Cont’d)
Name Direction Description