User guide

LogiCORE IP Block Memory Generator v6.1
64 www.xilinx.com DS512 March 1, 2011
Product Specification
• AXI4: Implements an AXI4 Interface Block Memory Generator Core.
Native Block Memory Generator First Screen
Component Name
The base name of the output files generated for the core. Names must begin with a letter and be
composed of any of the following characters: a to z, 0 to 9, and “_”. Names can not be Verilog or VHDL
reserved words.
Memory Type
Select the type of memory to be generated.
•Single-port RAM
•Simple Dual-port RAM
• True Dual-port RAM
•Single-port ROM
•Dual-port ROM
ECC Type
When targeting Kintex-7, Virtex-7, Virtex-6, Virtex-5, and Spartan-6 devices, and when the Simple dual-
port RAM memory type is selected, the ECC Type option becomes available. It provides the user the
choice to select the type of ECC required.
X-Ref Target - Figure 54
Figure 54: Block Memory Generator Main Screen