User guide

DS512 March 1, 2011 www.xilinx.com 65
Product Specification
LogiCORE IP Block Memory Generator v6.1
• Built-In ECC. When targeting Kintex-7, Virtex-7, Virtex-6 and Virtex-5 devices, and when the
selected ECC Type is BuiltIn_ECC, the built-in Hamming Error Correction is enabled for the
Kintex-7, Virtex-7, Virtex-6, and Virtex-5 FPGA architecture.
For the Kintex-7, Virtex-7, and Virtex-6 FPGA, the Use Error Injection Pins option is available for
selection if the ECC option is selected. This option enables error injection pins. On choosing this
option, additional options are available to have Single-Bit Error Injection (INJECTSBITERR),
Double-Bit Error Injection (INJECTDBITERR), or both. See Hamming Error Correction Capability,
page 5 for more information.
When using ECC, the following limitations apply:
• Byte-Write Enable is not available.
• All port widths must be identical.
• For Virtex-5 devices, No Change Operating mode is supported. For Kintex-7, Virtex-7, and
Virtex-6 devices, Read First Operating Mode is supported.
• The Use RST[A|B] Pin and the Output Reset Value options are not available.
• Memory Initialization is not supported.
• No algorithm selection is available.
• Soft ECC. When targeting Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices, and when the
selected ECC Type is Soft_ECC, soft error correction (using Hamming code) is enabled for the
Kintex-7, Virtex-7, Virtex-6, and Spartan-6 FPGAs.
The Use Error Injection Pins option is available for selection if the Soft ECC option is selected. This
option enables error injection pins. On choosing this option, additional options are available to
have Single-Bit Error Injection (INJECTSBITERR), Double-Bit Error Injection (INJECTDBITERR),
or both. See Soft Error Correction Capability and Error injection, page 46 for more information
about this option and the limitations that apply.
When using Soft ECC, the following conditions apply:
• Supports Soft ECC for data widths less than or equal to 64 bits
• Uses Hamming error code correction
- Single-bit errors are corrected
- Double-bit errors are detected
• Supports Simple Dual-port RAM memory type
• Supports optional Input and/or Output Registering stages
• Supported Block Memory Generator features include:
- Minimum Area, Fixed Primitive and Low Power Algorithms
- Mux Pipelining Stages
- Embedded Primitive Registers
- Core Output Registers
- Optional Enable Inputs
• Fully parameterized implementation for optimized resource utilization
Clocking Options
Select the Common Clock option when the clock (CLKA and CLKB) inputs are driven by the same
clock buffer.
Note:
For Kintex-7, Virtex-7, Virtex-6, and Spartan-6 devices with COMMON_CLOCK selected, WRITE_MODE
is set as READ_FIRST for Simple Dual Port RAM Memory type, otherwise WRITE_MODE is set as WRITE_FIRST.