User guide

LogiCORE IP Block Memory Generator v6.1
66 www.xilinx.com DS512 March 1, 2011
Product Specification
Write Enable
When targeting Kintex-7, Virtex-7, Virtex-6, Virtex-5, Virtex-4, Spartan-6, and Spartan-3A/3A DSP
devices, select whether to use the byte-Write enable feature. Byte size is either 8-bits (no parity) or 9-bits
(including parity). The data width of the memory will be multiples of the selected byte-size.
Algorithm
Select the algorithm used to implement the memory:
• Minimum Area Algorithm: Generates a core using the least number of primitives.
• Low Power Algorithm: Generates a core such that the minimum number of block RAM primitives
are enabled during a Read or Write operation.
• Fixed Primitive Algorithm: Generates a core that concatenates a single primitive type to
implement the memory. Choose which primitive type to use in the drop-down list.
Port Options Screen
Port A Options
•Memory Size
Specify the port A Write width and depth. Select the port A Read width from the drop-down list of
valid choices. The Read depth is calculated automatically.
•Operating Mode
Specify the port A operating mode.
•READ_FIRST
•WRITE_FIRST
X-Ref Target - Figure 55
Figure 55: Port A Options