User guide

LogiCORE IP Block Memory Generator v6.1
74 www.xilinx.com DS512 March 1, 2011
Product Specification
• If the memory width is an integral multiple of the width of the widest available primitive for the
chosen architecture, then the number of primitives used is calculated in the same way as the fixed
primitive algorithm. The width and depth ratios are calculated using the width and depth of the
widest primitive. For example, for a memory configuration of 2kx72, the width ratio is 2 and the
depth ratio is 4 using the widest primitive of 512x36. As a result, the total available primitives
used is 8.
• If the memory width is greater than an integral multiple of the widest primitive, then in addition
to the above calculated primitives, more primitives are needed to cover the remaining width. This
additional number is obtained by dividing the memory depth by the depth of the additional
primitive chosen to cover the remaining width. For example, a memory configuration of 17kx37
requires one 512x36 primitive to cover the width of 36, and an additional 16kx1 primitive to cover
the remaining width of 1. To cover the depth of 17K, 34 512x36 primitives and 2 16kx1 primitives
are needed. As a result, the total number of primitives used for this configuration is 36.
• If the memory width is less than the width of the widest primitive, then the smallest possible
primitive that covers the memory width is chosen for the solution. The total number of primitives
used is obtained by dividing the memory depth by the depth of the chosen primitive. For
example, for a memory configuration of 2kx32, the chosen primitive is 512x36, and the total
number of primitives used is 2k divided by 512, which is 4.
When using the minimum area algorithm, it is not as easy to determine the exact block RAM count.
This is because the actual algorithms perform complex manipulations to produce optimal solutions.
The optimistic estimate of the number of 18K block RAMs is total memory bits divided by 18k (the total
number of bits per primitive) rounded up. Given that this algorithm packs block RAMs very efficiently,
this estimate is often very accurate for most memories.
LUT Utilization and Performance
The LUT utilization and performance of the core are directly related to the arrangement of primitives
and the selection of output registers. Particularly, the number of primitives cascaded in depth to
implement a memory determines the size of the output multiplexer and the size of the input decoder,
which are implemented in the FPGA fabric.
Note:
Although the primary goal of the minimum area algorithm is to use the minimum number of block RAM
primitives, it has a secondary goal of maximizing performance – as long as block RAM usage does not increase.
Generating the AXI4 Interface Block Memory Generator Core
The AXI4 Interface Block Memory Generator GUI includes two additional screens followed by Native
BMG configuration screens:
• Interface Type Selection Screen
• AXI4 Interface Options