User guide

LogiCORE IP Block Memory Generator v6.1
76 www.xilinx.com DS512 March 1, 2011
Product Specification
AXI4 Interface Options
AXI4 Interface Options
• AXI4: Implements an AXI4 Block Memory Generator Core.
• AXI4-Lite: Implements an AXI4-Lite Block Memory Generator Core.
AXI4 Slave Options
• Memory Slave: Implements a AXI4 Interface Block Memory Generator Core in Memory Slave
mode
• Peripheral Slave: Implements a AXI4 Interface Block Memory Generator Core in Peripheral Slave
mode
ID Width Configurations
• ID Width: When enabled supports AWID/BID/ARID/RID generation, ID Width can be
configured from 1 to 16 bits
X-Ref Target - Figure 61
Figure 61: AXI4 Interface Options