User guide

LogiCORE IP Block Memory Generator v6.1
78 www.xilinx.com DS512 March 1, 2011
Product Specification
Output Registers
The Block Memory Generator optional output registers increase the performance of memories by
isolating the block RAM primitive clock-to-out delays and the data output multiplexer delays.
The output registers are only implemented for output ports. For this reason, when output registers are
used, a Single-port RAM requires fewer resources than a True Dual-port RAM. Note that the effects of
the core output registers are not fully illustrated due to the simple register wrapper used. In a full-scale
user design, core output registers may improve performance notably.
Table 23: Single Primitive Examples - Virtex-5 FPGAs
Memory
Type
Options
Width
x
Depth
Resource Utilization
Performance
(MHz)
Block RAMs
Shift
Regs
FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
36K 16K 8K
Tr ue
Dual-port
RAM
No Output
Registers
36x512 1 0 0 0 0 0 300
9x2k 0 1 0 0 0 0 325
Embedded Output
Registers
36x512 1 0 0 0 0 0 450
9x2k 0 1 0 0 0 0 450
Table 24: Single Primitive Examples - Virtex-4 FPGAs
Memory
Type
Options
Width x
Depth
Resource Utilization Performance (MHz)
Block
RAMs
16K
Shift
Regs
FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Virtex-4
True
Dual-port
RAM
No Output
Registers
36x512 1 0 0 0 300
9x2k 1 0 0 0 325
Embedded
Output Registers
36x512 1 0 0 0 400
9x2k 1 0 0 0 400
Table 25: Single Primitive Examples - Spartan-6 FPGAs
Memory
Type
Options
Width
x
Depth
Resource Utilization
Performance
(MHz)
Block RAMs
Shift
Regs
FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
36K 16K 8K
Tr ue
Dual-port
RAM
No Output
Registers
36x512 0 1 0 0 0 0 200
9x2k 0 1 0 0 0 0 225
Embedded Output
Registers
36x512 0 1 0 0 0 0 275
9x2k 0 1 0 0 0 0 300