User guide

DS512 March 1, 2011 www.xilinx.com 79
Product Specification
LogiCORE IP Block Memory Generator v6.1
In Virtex-6, Virtex-5, Virtex-4, and Spartan-6 architectures, the embedded block RAM may be utilized,
reducing the FPGA fabric resources required to create the registers.
Table 26: Virtex-6 Device Output Register Examples
Memory
Type
Width x
Depth
Output
Register
Options
Block RAM
Shift
Regs
FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance
(MHz)
36K 16K 8K
Single-port
RAM
17x5k
1300 3 18 325
Primitive 1 3 0 3 3 18 450
Core 1 3 0 0 20 18 325
Primitive, Core 1 3 0 3 20 18 450
Tru e
Dual-port
RAM
17x5k
1300 6 36 300
Primitive 1 3 0 6 6 36 450
Core 1 3 0 0 40 36 300
Primitive, Core 1 3 0 6 40 36 450
Table 27: Virtex-5 Device Output Register Examples
Memory
Type
Width x
Depth
Output
Register
Options
Block RAM
Shift
Regs
FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance
(MHz)
36K 16K 8K
Single-port
RAM
17x5k
1300 3 18 300
Primitive 1 3 0 3 3 18 450
Core 1 3 0 0 20 18 300
Primitive, Core 1 3 0 3 20 18 450
Tru e
Dual-port
RAM
17x5k
1300 6 36 300
Primitive 1 3 0 6 6 36 450
Core 1 3 0 0 40 36 300
Primitive, Core 1 3 0 6 40 36 450
Table 28: Virtex-4 Device Output Register Examples
Memory
Type
Width x
Depth
Output
Register
Option
Block
RAMs
16K
Shift
Regs
FFs LUTs
(1)
Performance (MHz)
Single-port
RAM
17x5k
-50330 275
Primitive 5 3 3 30 400
Core 5 0 20 30 275
Primitive, Core 5 2 22 32 400
Tru e
Dual-port
RAM
17x5k
-50660 275
Primitive 5 6 6 148 375
Core 5 0 40 142 250
Primitive, Core 5 6 40 148 375