User guide

LogiCORE IP Block Memory Generator v6.1
82 www.xilinx.com DS512 March 1, 2011
Product Specification
Table 35 shows examples of the resource utilization and the performance difference between them for
two selected configurations for Virtex-4 FPGA architecture.
Table 36 shows examples of the resource utilization and the performance difference between them for
two selected configurations for Spartan-6 FPGA architecture.
Table 35: Memory Algorithm Examples Virtex-4 Devices
Memory
Type
Width x
Depth
Algorithm Type
Resource Utilization
Performance (MHz)
Block
RAM
Shift
Regs
FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Single-port
RAM
17x5k
Minimum area 5 0 3 30 275
Fixed Primitive using
18x1k block RAM
50357 225
Low power 5 0 3 57 225
36x4k
Minimum area 8 0 1 36 275
Fixed Primitive using
36x512 block RAM
8 0 3 152 225
Low power 8 0 3 152 225
Table 36: Memory Algorithm Examples Spartan-6 Devices
Memory
Type
Width x
Depth
Algorithm
Type
Block RAM
Shift Regs FFs LUTs
(1)
1. LUTs are reported as the number of 4-input LUTs, and do not reflect the number of LUTs used as a route-through.
Performance
(MHz)
36K 16K 8K
Single-port
RAM
17x5k
Minimum area 0 5 0 0 3 19 175
Fixed Primitive
using 18x1k
block RAM
0 5 0 0 3 37 175
Low power 0 0 10 0 4 57 150
36x4k
Minimum area 0 8 0 0 1 18 175
Fixed Primitive
using 36x512
block RAM
0 8 0 0 3 76 150
Low power 0 0 16 0 4 170 125