User guide

LogiCORE IP Block Memory Generator v6.1
84 www.xilinx.com DS512 March 1, 2011
Product Specification
Native Block Memory Generator Supplemental Information
The following sections provide additional information about working with the Block Memory
Generator core.
• Low Power Designs: Provides information on the Low Power algorithm and methods that can be
followed by the user to optimize power consumption in block RAM designs.
• Compatibility with Older Memory Cores: Defines the differences between older memory cores
and the Block Memory Generator core.
• Construction of Smaller Memories: Explains the process of creating shallower or wider memories
using dual port block memory.
• Native Block Memory Generator SIM Parameters: Defines the SIM parameters used to specify the
core configuration.
• Output Register Configurations: Provides information optional output registers used to improve
core performance.
Low Power Designs
The Block Memory Generator core also supports a Low Power implementation algorithm. When this
option is selected, the configuration of the core is optimized to minimize dynamic power consumption.
This contrasts with the Minimum Area algorithm, which optimizes the core implementation with the
sole purpose of minimizing resource utilization.
The Low Power algorithm reduces power through the following mechanisms:
• Minimizing the number of block RAMs enabled for a Write or Read operation for a given memory
size.
• Unlike the Minimum Area algorithm, smaller block RAM blocks are not grouped to form larger
blocks in the Low Power algorithm. For example, two 9K block RAMs are not combined to form
an 18K block RAM in Spartan-6 devices, and two 18K block RAMs are not combined to form a 36K
block RAM in Virtex-5 devices.
• The “Always Enabled” option is not available to the user for the Port A and Port B enable pins.
This prevents the block RAMs from being enabled at all times.
• The NO_CHANGE mode is set as the default operating mode.
Table 41 and Table 42 compare power consumption and resource utilization for Low Power and
Minimum Area block memory implementations targeted to Virtex-5 devices and the Spartan-3 family
of devices. Estimated power consumption values were obtained using the XPE Spreadsheets from the
Power Solutions web page on Xilinx.com:
Table 40: AXI4-Lite Interface Block Memory Generator Spartan-6 FPGA
Memory
Type
Options
Width
X
Depth
Resource Utilization
Performance
(MHz)
Block RAMs
FFs LUTs
Occupied
Slices
36K 16K 8K
Simple
Dual Port
RAM
Memory
Slave
32x1024 - 2 0 25 45 18 219
64x512 - 2 0 24 43 20 217
Peripheral
Slave
32x1024 - 2 0 25 45 18 222
64x512 - 2 0 24 43 20 215