User guide

LogiCORE IP Block Memory Generator v6.1
86 www.xilinx.com DS512 March 1, 2011
Product Specification
• The Low Power algorithm disables the “Always Enabled” option for the Port A and Port B enable
pins, and the user is forced to have these pins at the output (the “Use EN[A|B] Pin” option). These
pins must not be permanently tied to ‘1’ if it is desired that power be conserved. Each port’s enable
pin must be asserted high only when that port of the block RAM needs to be accessed.
• Use of output registers improves performance, but also increases power consumption. Even if
used in the design, the output registers should be disabled when the block RAMs are not being
accessed.
• The user can choose the operating mode even in the Low Power algorithm based upon design
requirements; however it is recommended that the default operating mode of the Low Power
algorithm (NO_CHANGE mode) be used. This mode results in lower power consumption as
compared to the WRITE_FIRST and READ_FIRST modes.
Compatibility with Older Memory Cores
The Block Memory Generator Migration Kit can be used to migrate from legacy memory cores (Dual
Port Block Memory and Single Port Block Memory cores) and older versions of the Block Memory
Generator core to the latest version of the Block Memory Generator core.
For information about using the Migration Kit, see the Block Memory Generator Migration Kit Product
Page.
Auto Upgrade Feature
The Block Memory Generator core has an auto upgrade feature for updating older versions of the Block
Memory Generator core to the latest version. The auto upgrade feature can be seen by right clicking the
already generated older version of Block Memory Generator core in the Project IP tab of CORE
Generator.
There are wo types of auto upgrades:
• Upgrade Version and Regenerate (Under Current Project Settings): Upgrades an older Block
Memory Generator core to any intermediate version. The supported intermediate versions include
2.4, 2.7, 2.8, 3.1, 3.2, 3.3, 4.1, 4.2 and 4.3 of the Block Memory Generator.
• Upgrade to Latest Version and Regenerate (Under Current Project Settings): Upgrades an older
Block Memory Generator Core to the latest version. Any earlier version of Block Memory
Generator core can be upgraded to v6.1.
Construction of Smaller Memories
A single memory of a given depth can be used to construct two independent memories of half the
depth. This can be achieved by tying the MSB of the address of one port to ’0’ and the MSB of the
address of the second port to ’1’. This feature can be used only for memories that are at most one
primitive deep.
As an example, consider the construction of two independent 128x32 memories using a single 256x32
memory. Generate a 256x32 True Dual Port memory core in CORE Generator using the desired
parameters. Once generated, the MSB of ADDRA is connected to ’0’ and the MSB of ADDRB is
connected to’1’. This effectively turns a True Dual Port 256x32 memory (with both A and B ports
sharing the same memory space) into two single-port 128x32 memories, where port A is a single-port
memory addressing memory locations 0-127, and port B is a single-port memory addressing memory
locations 128-255. In this configuration, the two 128x32 memories function completely independent of
each other, in a single block RAM primitive. While initializing such a memory, the input COE file