User guide

DS512 March 1, 2011 www.xilinx.com 87
Product Specification
LogiCORE IP Block Memory Generator v6.1
should contain 256 32-bit wide entries. The first 128 entries initialize memory A, while the second 128
entries initialize memory B, as shown in Figure 62.
For construction of memories narrower than 32-bits, for example 19 bits, the widths of both ports A and
B can be set to 19 in the CORE Generator GUI. The cores are then connected the same way. The COE
entries must then be just 19 bits wide. Alternately, a 32-bit wide memory may be generated, and only
the least significant 19 bits may be used. COE entries in this case will be trimmed or padded with 0s
automatically to fill the appropriate number of bits.
For construction of memories shallower than 128 words, for example 23 words, simply use the first 23
entries in the memory, tying off the unused address bits to ’0’. Alternately, use the same strategy as
above to turn a True Dual Port 64-word deep memory into two 32-word deep memories.
Native Block Memory Generator SIM Parameters
Table 43 defines the SIM parameters used to specify the configuration of the core. These parameters are
only used to manually instantiate the core in HDL, calling the CORE Generator dynamically. This
parameter list does not apply to users that generate the core using the CORE Generator GUI.
X-Ref Target - Figure 62
Figure 62: Construction of Two Independent 128x32 Memories using a Single 256x32 Memory
Table 43: Native Interface SIM Parameters
SIM Parameter Type Values Description
1C_FAMILY String
“virtex4” “virtex5”
“spartan3”
Target device family
2C_XDEVICEFAMILY String
“virtex4” “virtex5”
“spartan3” “spartan3a”
“spartan3adsp”
Finest resolution target family
derived from the parent C_FAMILY
3 C_ELABORATION_DIR String Elaboration Directory
32
32
8
256x32
32
32
8
256x32
7
7
DINA
ADDRA
WEA
ENA
CLKA
DINB
ADDRB
WEB
ENB
CLKB
DOUTB
DOUTA
0
1