User guide

LogiCORE IP Block Memory Generator v6.1
88 www.xilinx.com DS512 March 1, 2011
Product Specification
4 C_MEM_TYPE Integer
0: Single Port RAM
1: Simple Dual Port RAM
2: True Dual Port RAM
3: Single Port ROM
4: Dual Port ROM
Type of memory
5 C_ALGORITHM Integer
0 (selectable primitive),
1 (minimum area),
2 (low power)
Type of algorithm
6 C_PRIM_TYPE Integer
0 (1-bit wide)
1 (2-bit wide)
2 (4-bit wide)
3 (9-bit wide)
4 (18-bit wide)
5 (36-bit wide)
6 (72-bit wide, single-port
only)
If fixed primitive algorithm is chosen,
determines which type of primitive to
use to build memory
7 C_BYTE_SIZE Integer 9, 8 Defines size of a byte: 9 bits or 8 bits
8 C_SIM_COLLISION_CHECK String
NONE,
GENERATE_X_ONLY,
ALL, WARNINGS_ONLY
Defines warning collision checks in
structural/unisim simulation model
9 C_COMMON_CLOCK Integer 0, 1
Determines whether to optimize
behavioral models for Read/Write
accesses and collision checks by
assuming clocks are synchronous.
It is recommended to set this option
to 0 when both the clocks are not
synchronous, in order to have the
models function properly.
10
C_DISABLE_WARN_BHV_C
OLL
Integer 0, 1
Disables the behavioral model from
generating warnings due to Read-
Write collisions
11
C_DISABLE_WARN_BHV_R
ANGE
Integer 0, 1
Disables the behavioral model from
generating warnings due to address
out of range
12 C_LOAD_INIT_FILE Integer 0, 1
Defined whether to load initialization
file
13 C_INIT_FILE_NAME String ""
Name of initialization file (MIF
format)
14 C_USE_DEFAULT_DATA Integer 0, 1
Determines whether to use default
data for the memory
15 C_DEFAULT_DATA String "0"
Defines a default data for the
memory
16
C_HAS_MEM_OUTPUT_RE
GS_A
Integer 0, 1
Determines whether port A has a
register stage added at the output of
the memory latch
17
C_HAS_MEM_OUTPUT_RE
GS_B
Integer 0,1
Determines whether port B has a
register stage added at the output of
the memory latch
Table 43: Native Interface SIM Parameters (Cont’d)
SIM Parameter Type Values Description