User guide

LogiCORE IP Block Memory Generator v6.1
90 www.xilinx.com DS512 March 1, 2011
Product Specification
42 C_INITB_VAL String “…”
Defines initialization/power-on value
for port B output
43 C_USE_BYTE_WEB Integer 0, 1
Determines whether byte-Write
feature is used on port B
This value is the same as
C_USE_BYTE_WEA, since there is
only a single byte Write enable
provided
44 C_WEB_WIDTH Integer 1 to 128 Defines width of WEB pin for port B
45 C_USE_ECC Integer 0,1
For Kintex-7, Virtex-7, Virtex-6, and
Virtex-5 FPGAs only. Determines
ECC options:
•0 = No ECC
•1 = ECC
46 C_RST_TYPE String
([“SYNC”, “ASYNC”] :
“SYNC”)
Type of Reset – synchronous or
asynchronous. This parameter
applies only for Spartan-6 devices.
47 C_RST_PRIORITY_A String ([“CE”, “SR”] : “CE”)
In the absence of output registers,
this selects the priority between the
RAM ENA and the RSTA pin. When
using output registers, this selects
the priority between REGCEA and
the RSTA pin.
48 C_RSTRAM_A Integer ([0,1] : 1)
Applicable for Kintex-7, Virtex-7,
Virtex-6, Spartan-3A DSP, and
Spartan-6 devices. If the value of
this generic is 1, both the memory
latch and the embedded primitive
output register of Port A are reset. If
this value is 0, then for Spartan-3A
DSP and Spartan-6 devices, the
primitive output register is built out of
fabric, and only the output register is
reset (the memory latch is not
reset). If this value is 0 for Kintex-7,
Virtex-7, and Virtex-6 devices, then
only the embedded output register
of the primitive is reset (the memory
latch is not reset).
Setting this option to 1 results in the
output reset value being asserted for
two clock cycles.
49 C_RST_PRIORITY_B String ([“CE”, “SR”] : “CE”)
In the absence of output registers,
this selects the priority between the
RAM ENB and the RSTB pin. When
using output registers, this selects
the priority between REGCEB and
the RSTB pin.
Table 43: Native Interface SIM Parameters (Cont’d)
SIM Parameter Type Values Description