User guide

DS512 March 1, 2011 www.xilinx.com 91
Product Specification
LogiCORE IP Block Memory Generator v6.1
AXI4 Interface Block Memory Generator SIM Parameters
50 C_RSTRAM_B Integer ([0,1] : 1)
Applicable for Kintex-7, Virtex-7,
Virtex-6, Spartan-3A DSP, and
Spartan-6 devices. If the value of
this generic is 1, both the memory
latch and the embedded primitive
output register of Port B are reset. If
this value is 0, then for Spartan-3A
DSP and Spartan-6 devices, the
primitive output register is built out of
fabric, and only the output register is
reset (the memory latch is not
reset). If this value is 0 for Kintex-7,
Virtex-7, and Virtex-6 devices, then
only the embedded output register
of the primitive is reset (the memory
latch is not reset).
Setting this option to 1 results in the
output reset value being asserted for
two clock cycles.
51 C_HAS_INJECTERR Integer ([0,1,2,3] : 0)
For Kintex-7, Virtex-7, and Virtex-6
FPGAs only. Determines the type of
error injection:
• 0 = No Error Injection
• 1 = Single-Bit Error Injection Only
• 2 = Double-Bit Error Injection
Only
• 3 = Both Single- and Double-Bit
Error Injection
52 C_USE_SOFTECC Integer 0,1
For Kintex-7, Virtex-7, Virtex-6, and
Spartan-6 FPGAs only. Determines
Soft ECC options:
• 0 = No Soft ECC
• 1 = Soft ECC
53
C_HAS_SOFTECC_INPUT_
REGS_A
Integer 0,1
Registers the input ports in the
design when Soft ECC is enabled:
• 0 = Registers not enabled
• 1 = Registers enabled
54
C_HAS_SOFTECC_OUTPU
T_REGS_B
Integer 0,1
Registers the input ports in the
design when Soft ECC is enabled:
• 0 = Registers not enabled
• 1 = Registers enabled
Table 44: AXI4 Interface SIM Parameters
SIM Parameter Type Values Description
1 C_FAMILY String
“virtex6” “virtex7”
“spartan6”
Target device family.
2 C_XDEVICEFAMILY String
“virtex6” “virtex7”
“spartan6”
Finest resolution target family.
3 C_ELABORATION_DIR String Elaboration Directory.
Table 43: Native Interface SIM Parameters (Cont’d)
SIM Parameter Type Values Description