User guide

DS512 March 1, 2011 www.xilinx.com 95
Product Specification
LogiCORE IP Block Memory Generator v6.1
54 C_RSTRAM_B Integer 0
Applicable for Kintex-7, Virtex-7,
Virtex-6, Spartan-3A DSP, and
Spartan-6 devices. If the value of
this generic is 1, both the memory
latch and the embedded primitive
output register of Port B are reset. If
this value is 0, then for Spartan-3A
DSP and Spartan-6 devices, the
primitive output register is built out of
fabric, and only the output register is
reset (the memory latch is not reset).
If this value is 0 for Kintex-7, Virtex-
7, and Virtex-6 devices, then only
the embedded output register of the
primitive is reset (the memory latch
is not reset).
Setting this option to 1 results in the
output reset value being asserted for
two clock cycles.
55 C_HAS_INJECTERR Integer ([0,1,2,3] : 0)
For Kintex-7, Virtex-7, and Virtex-6
FPGAs only. Determines the type of
error injection:
• 0 = No Error Injection
• 1 = Single-Bit Error Injection Only
• 2 = Double-Bit Error Injection
Only
• 3 = Both Single- and Double-Bit
Error Injection
56 C_USE_SOFTECC Integer 0
For Kintex-7, Virtex-7, Virtex-6, and
Spartan-6 FPGAs only. Determines
Soft ECC options:
• 0 = No Soft ECC
• 1 = Soft ECC
57
C_HAS_SOFTECC_INPUT
_REGS_A
Integer 0
Registers the input ports in the
design when Soft ECC is enabled:
• 0 = Registers not enabled
• 1 = Registers enable
58
C_HAS_SOFTECC_OUTPUT
_REGS_B
Integer 0
Registers the input ports in the
design when Soft ECC is enabled:
• 0 = Registers not enabled
• 1 = Registers enabled
59 C_SIM_COLLISION_CHECK String
NONE,
GENERATE_X_ONLY,
ALL,
WARNINGS_ONLY
Defines warning collision checks in
structural/UniSim simulation model.
Table 44: AXI4 Interface SIM Parameters (Cont’d)
SIM Parameter Type Values Description