User guide

DS512 March 1, 2011 www.xilinx.com 97
Product Specification
LogiCORE IP Block Memory Generator v6.1
For Kintex-7, Virtex-7, and Virtex-6, when only Register Port [A|B] Output of Memory Primitives and
the corresponding Use RST[A|B] Pin are selected, the special reset behavior (option to reset the
memory latch, in addition to the primitive output register) becomes available. For more information on
this reset behavior, see Special Reset Behavior, page 39.
Kintex-7, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA: Memory with Primitive and
Core Output Registers
With both Register Port [A|B] Output of Memory Primitives and the corresponding Register Port
[A|B] Output of Memory Core selected, a memory core is generated with the Kintex-7, Virtex-7, Virtex-
6, Virtex-5 or Virtex-4 FPGA embedded output registers and a register on the output of the core for the
selected port(s), as shown in Figure 64. This configuration may provide improved performance for
building large memory constructs.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core
X-Ref Target - Figure 64
Figure 64: Kintex-7, Virtex-7, Virtex-6, Virtex-5, or Virtex-4 FPGA Block Memory Generated with
Register Port [A|B] Output of Memory Primitives and Register Port [A|B] Output of Memory
Core Enabled
Block Memory Generator Core
Core
Output
Registers
Latches
Latches
FALSE
Block RAM Primitives
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
Latches
EN
Use REGCE Pin
REGCE
MUX
CLK
RST
DOUT
CE
DQ
CE
R*
DQ
R* : The reset (R) of the flop is gated by CE
TRUE