User guide

DS512 March 1, 2011 www.xilinx.com 99
Product Specification
LogiCORE IP Block Memory Generator v6.1
Kintex-7, Virtex-7, and Virtex-6 FPGAs: Memory with Primitive Output Registers and
with Special Reset Behavior option
When Register Port [A|B] Output of Memory Primitives, Use RSTA Pin (set/reset pin) or Use RSTB Pin
(set/reset pin), and the special reset behavior (to reset the memory latch besides the primitive output
register) are selected, then the input reset signal is connected to both the RSTRAM and RSTREG pins of
the Kintex-7, Virtex-7, and Virtex-6 devices’ block RAM primitive, as illustrated in Figure 66.
Port A or Port B
 Register Port A Output of Memory Primitives  Register Port B Output of Memory Primitives
 Register Port A Output of Memory Core  Register Port B Output of Memory Core
 Use RSTA Pin (set/reset pin)  Use RSTB Pin (set/reset pin)
 Reset Memory Latch  Reset Memory Latch
X-Ref Target - Figure 66
Figure 66: Kintex-7, Virtex-7, and Virtex-6 Block Memory Generated with Register Port [A|B]
Output of Memory Primitives Enabled and with Special Reset Behavior
Block Memory Generator Core
Latches
Latches
Utilized Block RAM Primitives
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
Latches
CE
SSR*
Block RAM
Embedded
Output Registers
Latches
EN
Use REGCE Pin
REGCE
MUX
CLK
RST
DOUT
CE
DQ
S* : The synchronous reset (S) of the flop is gated by CE
S*
RSTRAM
RSTREG
FALSE
TRUE