Datasheet

ManualsBrandsRamtron ManualsMemory ICsFRAM 8 k x 8 Bit SO-8

Preliminary

This is a product that has fixed target specifications but are subject Ramtron International Corporation

to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-FRAM, (719) 481-7000

Rev. 1.3 www.ramtron.com

Feb. 2011 Page 1 of 12

FM24C64B

64Kb Serial 5V F-RAM Memory

Features

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits

• High Endurance 1 Trillion (10

) Read/Writes

• 38 Year Data Retention

• NoDelay™ Writes

• Advanced High-Reliability Ferroelectric Process

Fast Two-wire Serial Interface

• Up to 1 MHz maximum bus frequency

• Direct hardware replacement for EEPROM

• Supports legacy timing for 100 kHz & 400 kHz

Low Power Operation

• 5V operation

• 100 µA Active Current (100 kHz)

• 4 µA (typ.) Standby Current

Industry Standard Configuration

• Industrial Temperature -40° C to +85° C

• 8-pin “Green”/RoHS SOIC (-G)

Description

The FM24C64B is a 64-kilobit nonvolatile memory

employing an advanced ferroelectric process. A

ferroelectric random access memory or FRAM is

nonvolatile and performs reads and writes like a

RAM. It provides reliable data retention for 38 years

while eliminating the complexities, overhead, and

system level reliability problems caused by

EEPROM and other nonvolatile memories.

The FM24C64B performs write operations at bus

speed. No write delays are incurred. Data is written to

the memory array in the cycle after it has been

successfully transferred to the device. The next bus

cycle may commence immediately without the need

for data polling. The FM24C64B is capable of

supporting 10

read/write cycles, or a million times

more write cycles than EEPROM.

These capabilities make the FM24C64B ideal for

nonvolatile memory applications requiring frequent

or rapid writes. Examples range from data collection

where the number of write cycles may be critical, to

demanding industrial controls where the long write

time of EEPROM can cause data loss. The

combination of features allows more frequent data

writes with less overhead for the system.

The FM24C64B provides substantial benefits to users

of serial EEPROM, yet these benefits are available in

a hardware drop-in replacement. The FM24C64B is

available in an industry standard 8-pin SOIC package

and uses a familiar two-wire protocol. The

specifications are guaranteed over an industrial

temperature range of -40°C to +85°C.

Pin Configuration

VSS

VDD

SCL

SDA

Pin Names Function

A0-A2 Device Select Address

SDA Serial Data/address

SCL Serial Clock

WP Write Protect

VSS Ground

VDD Supply Voltage

Ordering Information

FM24C64B-G “Green”/RoHS 8-pin SOIC

FM24C64B-GTR “Green”/RoHS 8-pin SOIC,

Tape & Reel

Summary of content (12 pages)

PAGE 1
Preliminary FM24C64B 64Kb Serial 5V F-RAM Memory Features 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 38 Year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface • Up to 1 MHz maximum bus frequency • Direct hardware replacement for EEPROM • Supports legacy timing for 100 kHz & 400 kHz Description The FM24C64B is a 64-kilobit nonvolatile memory employing an advanced ferroel
PAGE 2
FM24C64B Counter Address Latch 1,024 x 64 FRAM Array 8 SDA Serial to Parallel Converter Data Latch SCL WP Control Logic A0-A2 Figure 1. FM24C64B Block Diagram Pin Description Pin Name A0-A2 I/O Input SDA I/O SCL Input WP Input VDD VSS Rev. 1.3 Feb. 2011 Supply Supply Pin Description Address 2-0: These pins are used to select one of up to 8 devices of the same type on the same two-wire bus.
PAGE 3
FM24C64B Overview Two-wire Interface The FM24C64B is a serial FRAM memory. The memory array is logically organized as a 8,192 x 8 bit memory array and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C64B and a serial EEPROM with the same pinout relates to its superior write performance. The FM24C64B employs a bi-directional two-wire bus protocol using few pins and little board space.
PAGE 4
FM24C64B Figure 3. Data Transfer Protocol Stop Condition A Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition.
PAGE 5
FM24C64B Memory Operation Device Select Slave ID 1 0 1 0 A2 A1 A0 R/W 7 6 5 4 3 2 1 0 Figure 4. Slave Address Addressing Overview After the FM24C64B (as receiver) acknowledges the device address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The first is the MSB (upper byte). Since the device uses only 13 address bits, the value of the upper three bits are don’t care.
PAGE 6
FM24C64B Start By Master S Stop Address & Data Slave Address 0 A Address MSB By FM24C64B A Address LSB A Data Byte A P Acknowledge Figure 5. Byte Write Start S By FM24C64B Stop Address & Data By Master Slave Address 0 A Address MSB A Address LSB A Data Byte A Data Byte A P Acknowledge Figure 6. Multiple-Byte Write Read Operation There are two basic types of read operations. They are current address read and selective address read.
PAGE 7
FM24C64B set to a 1. The operation is now a current address read. master issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the device address LSB Start By Master No Acknowledge Address Stop S Slave Address By FM24C64B 1 A Data Byte Acknowledge 1 P Data Figure 7.
PAGE 8
FM24C64B Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +7.0V -1.0V to +7.0V and VIN < VDD+1.
PAGE 9
FM24C64B AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max fSCL SCL Clock Frequency 0 100 0 400 0 1000 tLOW Clock Low Period 4.7 1.3 0.6 tHIGH Clock High Period 4.0 0.6 0.4 tAA SCL Low to SDA Data Out Valid 3 0.9 0.
PAGE 10
FM24C64B AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels Input rise and fall times Input and output timing levels 0.1 VDD to 0.9 VDD 10 ns 0.5 VDD 5.5V 1700 Ω Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections.
PAGE 11
FM24C64B Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXX-P LLLLLLL RICYYWW Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C64B, “Green” SOIC package, Year 2010, Work Week 47 FM24C64B-G A00002G1 RIC1047 Rev. 1.3 Feb.
PAGE 12
FM24C64B Revision History Revision 1.0 1.1 1.2 1.3 Rev. 1.3 Feb. 2011 Date 11/10/2010 12/20/2010 2/7/2011 2/15/2011 Summary Initial Release Changed VIH (max) to VDD+0.3V. Added ESD ratings. Changed tPU and tVF spec limits.