Specifications

ManualsBrandsRandell ManualsKitchen AppliancesRANFG IC-5

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iC-v82

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Summary of content (34 pages)

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).42/$5#4)/. 4HIS SERVICE MANUAL DESCRIBES THE LATEST SERVICE INFORMATION FOR THE )# 6 6(& 42!.3#%)6%2 AT THE TIME OF PUBLICATION -/$%, 6%23)/. 39-"/, 53! %52 )# 6 #3! %80 "!44%29 0!#+ "0 . "0 . "0 . "0 . "0 . "0 . "0 . "0 . "0 . "0 . ;53! = ;53! = ;53! = ;%52 = ;%52 = ;%52 = ;#3! = ;#3! = ;#3! = ;%80 = ;%80 = ;%80 = ;%80 = "0 . "0 .
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TABLE OF CONTENTS SECTION 1 SPECIFICATIONS SECTION 2 INSIDE VIEWS SECTION 3 DISASSEMBLY INSTRUCTIONS SECTION 4 CIRCUIT DESCRIPTION 4-1 RECEIVER CIRCUITS ................................................................................................... 4 - 1 4-2 TRANSMITTER CIRCUITS ............................................................................................ 4 - 2 4-3 PLL CIRCUITS ...................................................................................................
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SECTION 1 SPECIFICATIONS GENERAL • Frequency range : TX 144.000–148.000 MHz 144.000–146.000 MHz 136.000–174.000 MHz* RX 136.000–174.000 MHz* 144.000–146.000 MHz • Operating temperature range : –10°C to 60°C; +14°F to +140°F • Operating mode : F2D, F3E, F7W* • Frequency stability : ±2.5 ppm (–10°C to +60°C; +14°F to +140°F) [USA] [EUR] [EXP], [CSA] [USA], [EXP], [CSA] [EUR] *Specifications are guaranteed within 144.000 to 148.000 MHz range only.
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SECTION 2 INSIDE VIEWS • MAIN UNIT Top view TX drive amplifier (Q2: RD01MUS1) Bottom view Power amplifier (Q1: RD12MVS1) Pre-emphasis circuit (IC3: LMV324IPWR) Antenna switch (D2: MA77) 1st IF mixer (Q13: 3SK318YB) RF amplifier (Q12: 3SK318YB) CPU5 regulator (IC12: S-812C50AMC) FM IF IC (IC2: TA31136FN) IF amplifier (Q14: 2SC5006) PLL IC (IC19: MB15E03S LPFV1) VCO circuit MIC mute/Analog switch (IC4: CD4066BPWR) AF power amplifier (IC5: NJM2070M) DA converter (IC10: M62363FP) CPU (IC8: M30220FC
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SECTION 3 DISASSEMBLY INSTRUCTIONS 1. Removing the chassis panel 2. Removing the MAIN unit. q Remove the knob A and jack cap B. w Unscrew 1 nut C. e Unscrew 2 screws D (2 × 10 mm, black) and 2 screws E (2 × 4 mm, black) from the chassis. r Unplug the speaker connector (J6). t Take off the chassis in the direction of the arrow. q Remove the Jack seal F. w Unsolder 4 points G of the shield cover. e Unscrew 1 nut H and 2 screws I (2 × 4 mm, black).
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SECTION 4 CIRCUIT DESCRIPTION The 1st IF signal from the 1st mixer is passed through the crystal filter (FI1) to suppress unwanted signals, and the limiter (D63) and then applied to the 1st IF amplifier (Q14). 4-1 RECEIVER CIRCUITS 4-1-1 ANTENNA SWITCHING CIRCUIT The antenna switching circuit toggles receive line and transmit line. This circuit does not allow transmit signals to enter the receiver circuits. The amplified 1st IF signal is applied to the FM IF IC (IC2, pin 16).
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The signals from the pre-emphasis circuit are passed through the analog switch (IC4, pins 3, 4) and LPF (IC3, pins 13, 14). The signals from the LPF are passed through another analog switch (IC4, pins 8, 9), digital/analog switch (IC15, pins 8, 9 and pins 3, 4) and D/A converter (IC10, pins 21, 22) to adjust its level. The level adjusted signals from the D/A converter are applied to the modulator circuit (D61). 4-1-6 SQUELCH CIRCUIT Squelch circuit mutes AF output signal when no signals are received.
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4-3 PLL CIRCUITS 4-3-3 RECEIVE LOOP 4-3-1 GENERAL The generated 1st LO signal is applied to the PLL IC (IC19, pin 8) via the buffer-amplifiers (Q5, Q75) and is divided at the prescaler section and the programmable divider section, then applied to the phase detector section. PLL circuits control the VCO circuit. IC19 is a PLL IC and contains prescaler, programmable counter, programmable divider, phase detector, charge pump in its package.
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4-5 POWER SUPPLY CIRCUITS PIN NUMBER 4-5-1 VOLTAGE LINES LINE DESCRIPTION PORT NAME DESCRIPTION 26 NOIS Input port for "NOIS" signal. VCC The voltage from the attached battery pack. 28 ESDA I/O port for EEPROM (IC7). CPU5 Common 5 V for the CPU (IC8) converted from the VCC line at the CPU5 regulator circuit (IC12). 29 ESCK Outputs clock signal for EEPROM (IC7). Common 5 V line converted from the VCC line at the SW5 regulator circuit (Q55–Q57, D39) controlled by the "PWRON" signal.
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PIN NUMBER PORT NAME 70 PLLSTB DESCRIPTION Outputs PLL strobe signal. AFON Outputs AF regulator (Q15, Q16) control signal. HIGH : While emitting audio 72 DUSE Outputs LPF cut-off frequency control signal to the CTCSS switch (Q38). LOW : When CTCSS or no signaling system is in use. HIGH : DTCS is in use. 73–76 KR0–KR3 78 UNLK 79 EMPHASIS Outputs emphasis switch (Q73) control signal. HIGH : During FM mode operation. 80 T5C Outputs T5 regurator (Q22) control signal.
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4-7 UT-118 CIRCUIT DESCRIPTION 4-8 UT-118 POWER SUPPLY CIRCUITS 4-7-1 RECEIVER CIRCUIT 4-8-1 VOLTAGE LINES The detected digital signals “FMDET” from the connected transceiver via the J301 (pin 22) are amplified at the buffer amplifier (IC251, pin 2). The amplified signals are applied to the GMSK modem circuit (IC252, pin 11), and are then applied to the CPU (IC204) as clock synchronizer digital signal.
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SECTION 5 ADJUSTMENT PROCEDURES 5-1 PREPARATION REQUIRED TEST EQUIPMENTS EQUIPMENT GRADE AND RANGE Output voltage EQUIPMENT GRADE AND RANGE Current capacity : 5.0 V DC 8.0 V DC : 1 A or more Standard signal generator (SSG) Frequency range : 0.1–300 MHz Output level : 0.1 µV to 32 mV (–127 to –17 dBm) RF power meter (terminated type) Measuring range Frequency range Impedance SWR : 0.1–20 W : 100–300 MHz : 50 Ω : Less than 1.2 : 1 Oscilloscope Frequency range : DC–20 MHz Measuring range : 0.
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S S S 5-2 IC-V82 ADJUSTMENT S 5-2-1 KEY OPERATION FOR THE ADJUSTMENT • Rotate [VOL] to adjust the value. • Push [D•CLR] key to store the adjustment value and move to next adjustment item. • Push [ ]/[ ] key to move to next adjustment item without changing the value. 5-2-2 FREQUENCY AND TRANSMIT ADJUSTMENT ADJUSTMENT ENTERING ADJUSTMENT MODE ADJUSTMENT CONDITION OPERATION • While pushing [ ], [ ] and [D•CLR] keys, turn power ON.
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5-2-3 RECEIVE ADJUSTMENT S ADJUSTMENT S SENSITIVITY ADJUSTMENT CONDITION OPERATION 1 • Connect an SSG to the antenna • Push [D•CLR] key. connector and set as; Frequency : 136.020 MHz Level : 0 dBµ* Modulation : 1 kHz Deviation : ± 3.5 kHz • Receiving 2 • Set the SSG as; Frequency : 147.980 MHz Level : 0 dBµ* Modulation : 1 kHz Deviation : ± 3.5 kHz • Receiving • Push [D•CLR] key. 3 • Set the SSG as; Frequency : 173.980 MHz Level : 0 dBµ* Modulation : 1 kHz Deviation : ± 3.
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5-3 UT-118 ADJUSTMENT • CONNECTION (BOTTOM VIEW) Power supply 5.0 V DC / 1 A Power supply 8.0 V DC / 1 A J301, Pin 14 Entering adjustment mode • ADJUSTMENT ADJUSTMENT ENTERING ADJUSTMENT MODE ADJUSTMENT CONDITION OPERATION • Connect the pin 14 of J301 to GND to enter the adjustment mode. CODEC FREQUENCY 1 • Connect the frequency counter to CP101 • Adjust C102 to set to 16.38400 MHz ±10 Hz. through a capacitor (1000 pF).
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SECTION 6 PARTS LIST 6-1 IC-V82 [MAIN UNIT] REF NO. [MAIN UNIT] ORDER NO. DESCRIPTION H/V M. LOCATION IC2 IC3 IC4 IC5 IC7 IC8 IC10 IC12 IC13 IC14 IC15 IC16 IC17 IC19 IC20 IC21 IC22 IC23 IC24 IC25 1110003490 1110006470 1130011770 1110002810 1130012430 1140012450 1190000350 1180002250 1130011770 1130011770 1130011770 1130011780 1110005310 1130011670 1130011800 1110006260 1180002680 1110006490 1180002690 1110006490 S.IC S.IC S.IC S.IC S.IC IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.REG S.
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[MAIN UNIT] [MAIN UNIT] REF NO. R61 R64 R66 R68 R69 R70 R71 R72 R75 R77 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 R93 R94 R95 R97 R98 R99 R100 R101 R102 R103 R104 R105 R107 R108 R112 R113 R114 R115 R117 R120 R121 R122 R123 R126 R127 R128 R130 R131 R132 R136 R137 R139 R141 R144 R148 R150 R155 R159 R160 R161 R162 R163 R164 R169 R170 R174 R176 R177 R178 R181 R182 R184 R185 R186 R187 R193 R194 R195 R196 R204 R205 R210 R222 R224 R225 R227 R228 R240 R244 R245 R246 R251 R252 R257 R258 ORDER NO.
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[MAIN UNIT] [MAIN UNIT] REF NO. ORDER NO.
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[MAIN UNIT] [MAIN UNIT] REF NO. ORDER NO. DESCRIPTION H/V M. LOCATION REF NO. C298 4550005980 S.TAN TEESVA 1A 475M8L B 109.9/18.4 C299 4030017730 S.CER ECJ0EB1E471K B 93.7/3 C300 4030017460 S.CER ECJ0EB1E102K B 84.7/29.9 C301 4030017460 S.CER ECJ0EB1E102K T 88.4/21.3 C303 4030017460 S.CER ECJ0EB1E102K T 103.1/29 C304 4030016950 S.CER ECJ0EB1A473K B 22.6/16.9 C305 4030017730 S.CER ECJ0EB1E471K T 111.2/36.6 C351 4030017570 S.CER ECJ0EC1H040B B 97.6/21.4 C369 4030017040 S.CER ECJ0EB1A333K B 49.2/36.
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6-2 OPTIONAL UNIT UT-118 [MAIN UNIT] REF NO. [MAIN UNIT] REF NO. ORDER NO. DESCRIPTION H/V M. LOCATION IC1 IC2 IC50 IC101 IC103 IC151 IC202 IC203 IC204 IC251 IC252 IC253 IC254 IC351 1180002390 1180002370 1130011630 1130008360 1130006890 1130010920 1130010460 1110005730 1140010770 1110005290 1110005430 1110006200 1130004200 1120002980 S.REG S.REG S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.IC S.
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SECTION 7 MECHANICAL PARTS AND DISASSEMBLY [CHASSIS PARTS] REF. NO. ORDER NO. [MAIN UNIT] DESCRIPTION QTY. REF. NO. ORDER NO. DESCRIPTION QTY.
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SECTION 8 SEMICONDUCTOR INFORMATION •TRANSISTORS AND FETS •DIODES 2SA1576A (Symbol: FA) 2SA1576S (Symbol: FS) 2SC4116BL (Symbol: LL) 2SB1132R (Symbol: BAR) B C E 2SC5006-T1 (Symbol: 24) E 2SC5085Y (Symbol: R6) B B 3SK318YB-TL-E (Symbol: YB) G1 G2 E RD01MUS1 (Symbol: K2) S D 3SK299-U73 (Symbol: U73) S G1 G D S S S D G C A C DA221 TL (Symbol: K) S C1 C MA742 (Symbol: M1U) A UNR9210J (Symbol: 8L) B UNR9213J (Symbol: 8C) B C2 C C C MA77 (Symbol: 4B) C MA8056-M (Sym
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SECTION 9 BOARD LAYOUTS MAIN UNIT • TOP VIEW The combination of this page and next page shows the unit layout in the same configuration as the actual P.C. Board. H0 H5 H10 H15 H20 H25 H30 H35 H40 H45 H50 H55 H60 H65 H70 H75 H80 H85 H90 H95 H100 H105 H110 H115 H120 H125 V45 V40 S801 ENCODER DN E V35 UP V30 BATT GND V25 V20 ANTENNA V15 V10 MIC OPT V5 2 1 V0 2 OPT 1 MIC AFOUT W5 CLONE SP. GND 9-1 EXT. MIC MIC GND SP1 SPEAKER J2 J3 EXT.
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• BOTTOM VIEW The combination of this page and previous page shows the unit layout in the same configuration as the actual P.C. Board.
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SECTION 10 BLOCK DIAGRAM • MAIN UNIT D64, D72: 1SS400 Q34: 2SK1069 UNLK UNLOCK DET DC AMP LVIN X4: CR-783 (15.3MHz) IC23: LMV321IDCK SW +5V AMP IC19: MB15E03SL IC24: S-812C36AMC D0 PLL IC REF OSC FC MOD LOOP FIL LO AMP VCO SW5V VCO SHIFT R5 FIN OPTION UNIT OSCO DIGI CTCSS Q75: 2SC5231 D58: MA2S077 Q77: UNR921NJ Q3: 2SC5085 Q2: RD12MUS1 PRE DRIVE TX/RX SW BUFF X3 BPF AMP D/A LOOP SW PWR AMP ANT SW PWR DET LPF D1: HVU131TRF D2: MA77 LPF Q74: 2SC5231 Tx: 136.000–174.
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IC24 S-812C36AMC C521 R460 0.001 18k C487 47p A T5 Q22 2SA1576A R457 10k 6 1 4.91V C471 C463 0.1 0.001 R488 22k R50 270k CP1 X4 CR-783 (15.3 MHz) R49 JPW L55 0.22µH 4 2 3 GND OUT C70 0.001 C497 5p R436 39k R469 1k R448 1.2k L43 82nH C474 0.1 R184 10k MOD MOD C475 0.001 R5 RMOD MODIN C386 7p R84 390 R81 470 IC2 TA31136FN 1 2 3 4 5 6 7 8 C422 0.1 R5 16 15 14 13 12 11 10 9 MIXIN GND N-REC N-DET RSSI IFOUT QUAD AFOUT C116 82p D63 DA221 C417 0.1 R387 3.
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SECTION 12 UT-118 DIGITAL UNIT (OPTIONAL UNIT) 12-1 UT-118 BOARD LAYOUT • TOP VIEW • BOTTOM VIEW V30 V30 V25 16 25 1 20 V25 1 1 100 26 17 1 8 4 5 64 J301 V20 1 PTTIN V20 10 11 V15 32 50 1 4 8 1 V5 24 1 75 V5 8 5 12 48 76 51 16 13 49 33 V10 GND 30 PTTOUT 5V MICOUT VCC_8V MICIN — 232TX — BUSY 232RX V15 — RXMUTE SICO FMDET OPT1 AFOUT OPT2 REFMOD OPT3 CSS GND — V10 OPV3 OPSO OPV2 SI OPV1 OPSCK 16 15 To Main unit J5 9 14 - 1 V0 V0 H0 H5 H10 H15 H20 H25 H30 H35 H
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12-2 UT-118 SEMICONDUCTOR INFORMATION 12-3 UT-118 BLOCK DIAGRAM • TRANSISTORS AND FET’S 2SA1586 GR (Symbol: SG) DTC144EUA T106 (Symbol: 26_) &/2 &-?42!.#%6%2 /04)/. #/..%#4/2 XP4312 (Symbol: 7T) &,!3( 72)4%2 B B C C E E E1 C1 B1 B2 C2 E2 %XPLANATORY NOTES 1 80 1 80 6/,4!'% ,).% 48 ,).% ,%6%, #/.6%24 28 ,).% &/2 &-?42!.#%6%2 #05 #/.42/, ,).% &?28$ 2%3 48$ 48$? 28$? $!4! "53 ,).
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12-4 UT-118 VOLTAGE DIAGRAM 3.3V SI ARXD ARES C58 0.1 C150 1 VCC_8V C205 0.1 1 2 4 C156 0.1 R216 47k R217 47k R212 47k MCLK P85 P86 P87 TXD RXD ACQ NMI 4 ASTB ARXD ARES ARES ATXD ACLK C154 0.1 C155 0.1 C153 0.1 R151 1k 3 TXD_2 4 TXDT RXDT RXCK TXCK TXD_2 RXD_2 RMUTE ACQ MCLK TXCK RXCK RXDT TXDT 3 BUSY PSAVE Q202 DTC144EU PSAVE CP101 2 R103 1k P01 PTTIN 3 5 1 2 R211 47k C203 0.
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