Data Sheet

Page 14
50 BT_WAKE_HOST O
BT_WAKE_HOST (GPIO14)
9.Schematic design guide
1. RF reserves C-L-C components for impedance matching fine tuning.
2. SDIO 3.0: VDDIO connects 1.8V.
3. Pull high resistance is reserved for SDIO signal line.
4. BT HCI is the UART interface, the connection is as follows, UART_RX is
recommended to add Pull High resistor.
Schematics are long-term confidential information