Eclipse3 Series User’s Manual Graphics Boards for PMC, PCI and CompactPCI Compatible Computers Rastergraf Rastergraf, Inc. 1804-P SE First St. Redmond, OR 97756 (541) 923-5530 FAX (541) 923-6475 web: http://www.rastergraf.com Release 2.
Table of Contents INTRODUCTION...................................................................................... Introduction-1 GETTING HELP .........................................................................................................................Introduction-2 BOARD REVISIONS ...................................................................................................................Introduction-2 NOTICES .............................................................................
Rastergraf Figures and Tables Table 1-1 Table 1-2 Table 1-3 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Eclipse3 SDL Platform Display Timing Specifications................................. 1-9 Eclipse3 FCode/Solaris Platform Display Timing Specifications................ 1-10 Eclipse3 VGA/Windows Platform Display Timing Specifications ............. 1-10 Rastergraf Ruggedization Levels Chart................................
Rastergraf Introduction This manual provides information about how to configure, install, and program the Rastergraf Eclipse3 128-bit graphics display controllers. Software support is available for Solaris, Linux, VxWorks, LynxOS, and Windows 2000 and XP. They are available for PMC PCI, and CompactPCI compatible computers.
Rastergraf Getting Help This installation manual gives specific steps to take to install your Rastergraf graphics board. There are, however, variables specific to your computer configuration and monitor that this manual cannot address. Normally, the default values given in this manual will work. If you have trouble installing or configuring your system, first read Chapter 4, “Troubleshooting”.
Rastergraf Notices Information contained in this manual is disclosed in confidence and may not be duplicated in full or in part by any person without prior approval of Rastergraf. Its sole purpose is to provide the user with adequately detailed documentation to effectively install and operate the equipment supplied. The use of this document for any other purpose is specifically prohibited. The information in this document is subject to change without notice.
Rastergraf Conventions Used In This Manual The following list summarizes the conventions used throughout this manual. Code fragments Commands or program names System prompts and commands Keyboard usage Note Note boxes contain information either specific to one or more platforms, or interesting, background information that is not essential to the installation. Caution Caution boxes warn you about actions that can cause damage to your computer or its software.
Rastergraf Chapter 1 General Information 1.1 Introduction The Rastergraf Eclipse3 is part of Rastergraf ’s broad line of graphics modules for use in PMC, PCI, VME, and CompactPCI computers. For information about all of Rastergraf ’s products, please contact Rastergraf Worldwide Sales at (541) 923-5530 or consult Rastergraf ’s web page at http://www.rastergraf.com. The Eclipse3 uses a Rastergraf Borealis 2D/3D 128-bit graphics accelerator.
Rastergraf 1.2 Functional Description As an aid to understanding the Eclipse3, a block diagram is provided at the end of this section.
Rastergraf 1.2.1 Borealis Graphics Controller The Rastergraf Borealis 2D/3D graphics controller chip is a 128-bit graphics controller with accelerated 2D and 3D patterned lines and shaded triangles, Z buffer, and 3D volume clipping. It provides a high performance 33/66 MHz PCI 2.1 compliant interface with no additional external logic required.
Rastergraf The Borealis design is based on technology licensed by Rastergraf from S3/Number Nine. The chip itself is manufactured for Rastergraf by LSI Logic using LSI’s .35u G-10P ASIC process. The Borealis graphics controller is implemented using a highly pipelined graphic processor architecture. This architecture allows for high performance 2D and 3D rendering.
Rastergraf 1.2.2 DVI Digital Output The Eclipse3 may be ordered with a DVI-compliant transmitter which provides high quality 24-bit true color digital output over twisted pair cables up to 5 meters in length. This length may be increased by using shielded twin-ax or fiber-optic cables. Displays ranging up to 1600 x 1200 are supported. Three TMDS data channels send data at 1.65 Gbps per channel. Connections to the Eclipse3 are made through the front DVI-I connector.
1-6 General Information VGA RAMDAC 33/66 MHz PCI 2.
Rastergraf 1.3 Additional References You can find Rastergraf documentation and technical literature on the Rastergraf web page (http://www.rastergraf.com). The CompactPCI Specification – PICMG R2.0 R3.0, the CompactPCI Hot Swap Specification – PICMG 2.1 R2.0 and the CompactPCI Hot Swap Infrastructure Interface Specification PICMG 2.12 R1.0 standards and other information are available from PICMG: Web Page: https://www.picmg.org/index.stm The PCI Local Bus 2.
Rastergraf 1.4 Specifications for the Eclipse3 The Eclipse3 are available in several configurations: Analog: Borealis graphics controller and 16 or 32 MB display memory DVI: Borealis graphics controller and 16 or 32 MB display memory and DVI-I DVI/VGA connector. Note that the Eclipse3CPCI and Eclipse3PCI have both VGA and DVI-I connectors. Special Order: LEDs, LM75 thermal sensor, Serial EEPROM, Conformal Coating, Extended Temperature. Rear Panel I/O (CPCI J2).
Rastergraf Scroll, Pan, and Zoom: Scroll - single line (smooth scroll). Pan - anywhere on 16 byte boundaries Zoom: horizontal: 2, 4, 8, 16, vertical: 2, 3 ,...,15, 16 Digital Output (Optional): The Eclipse3 can supply a digital output using a THine THC63DV164 DVI encoder. The Borealis Video Out Bus, which supplies TTL level RGB and Sync, is sampled and multiplexed and driven onto 4 differential pairs.
Rastergraf Table 1-2 Eclipse3 FCode/Solaris Platform Display Timing Specifications Active Display Analog/ DVI Bits per Pixel Vertical Refresh Horizontal Refresh Pixel Clock 640 x 480 Both 8 9 8, 16, 32 60 Hz 75 Hz 31.5 KHz 37.5 KHz 25.2 MHz 31.5 MHz 800 x 600 Both 6 7 8, 16, 32 60 Hz 75 Hz 37.9 KHz 46.9 KHz 40 MHz 49.5 MHz 1024 x 768 Both 0 1 8, 16, 32 60 Hz 75 Hz 48.4 KHz 60.0 KHz 65.0 MHz 78.8 MHz 1152 x 864 Both 2 3 8, 16, 32 60 Hz 75 Hz 56.7 KHz 67.5 KHz 87.
Rastergraf Fuse Element: The +5V supplied to the front panel connectors is protected by a Positive Temperature Coefficient (PTC) resistor. It resets automatically when the overload is removed.
Rastergraf Environment: Temperature: Humidity: Enhanced Status: 0 to 70 degrees C, operating -55 to +85 degrees C, storage 5% to 90%, non-condensing Special order features include: Three LEDs that can be driven by host CPU software. A 2Kb Serial EEPROM stores the serial number, display timing information, and customer specific parameters. An LM75 thermal sensor provides limit flags and real-time temperature read-back.
Rastergraf Ruggedization Levels: The following table shows the standard ruggedization levels. At the time of writing, complete shock and vibration testing has not been performed, but some boards have been tested enough to expect full acceptance is possible. Please contact Rastergraf Sales if you need this information.
Rastergraf 1.5 Eclipse3 Connectors and Cables There are two possible connector locations on the front panel of the Eclipse3 graphics boards. Note: Due to front panel space limitations, the PMC board can have either the VGA or the DVI connector installed. The PCI and CompactPCI boards have both installed. The Eclipse3 “Standard” versions use a standard 15-pin VGA compatible connector. RGBHV (Red, Green, Blue, and Horizontal and Vertical sync) and DDC/DDA monitor control signals are supplied.
Rastergraf 1.5.1 VGA Connector The graphics board analog output is provided on a standard VGA style compressed 15 pin D-Sub. Alternatively, when the DVI-I connector is used (see Section 1.5.2), an adapter (Molex 88741-8700) can be used to supply analog video to a standard VGA computer side connector. In either case, an “Autoscan” type monitor is used. You must use the correct initialization, since a VGA monitor depends on the sync polarities to determine operating frequency.
Rastergraf Table 1-4 Analog (VGA) Video Connector Pinout VGA Pin Description Ground Type 1 Red 75 ohm Coax with pin 6 2 Green 75 ohm Coax with pin 7 3 Blue 75 ohm Coax with pin 8 4 not used 5 DDC Ground Circuit Ground 6 Red Ground Circuit Ground 7 Green Ground Circuit Ground 8 Blue Ground Circuit Ground 9 Fused +5 Volts, .
Rastergraf 1.5.2 DVI-I Connector The DVI front panel connector is a DVI-I (analog/digital) (http://www.ddwg.org/) connector. DVI uses the DVI TMDS encoded data format, which allows longer data cables and reduces emitted noise. Each of the three differential pairs carries nine digital video (TTL) lines. A separate pair carries the PLL clock for the TMDS system. TMDS requires that the length of all pairs must be closely matched. The Borealis boards use a THine THC63DV164 DVI transmitter.
Rastergraf 1.5.
Rastergraf 1.5.4 Connections to the PCI Bus SIDE A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 n/c n/c n/c JTAGTDIOH VCC (5V) PINTAL n/c VCC (5V) n/c byp (Vio) n/c keyway keyway n/c PPCIRSTL byp (Vio) PCIGNTL GND n/c PAD30H VDD (3.3V) PAD28H PAD26H GND PAD24H PIDSELH VDD (3.
Rastergraf 1.5.
Rastergraf 1.5.5 J1 Connections to the CompactPCI Bus A B C D 1 VCC (5V) 1 byp (-12V) 1 n/c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 n/c INTA# n/c n/c PCIREQ# AD[30] AD[26] CBE[3]# AD[21] AD[18] keyway keyway keyway VDD (3.3V) DEVSEL# VDD (3.3V) n/c VDD (3.3V) AD[12] VDD (3.3V) AD[07] VDD (3.
Rastergraf 1.5.
Rastergraf 1.6 Monitor Requirements Rastergraf graphics boards can be used with a variety of monitors. For best performance a monitor should have the following features: • VGA compatible 5 Wire RGB with separate TTL horizontal and vertical sync or 3 Wire RGB with sync on green (see note below) • Switchable Termination (for monitor loopthrough) • Height, pincushion, width, phase, and position controls • Autotracking horizontal and vertical synchronization • See tables in Section 1.
Rastergraf 1.7 Configuration Information The basic graphics board includes: • • • • • Rastergraf Borealis Graphics Processor with 8, 16, or 32 bit/pixel 16 MB SGRAM hardware interrupts, pan, scroll, and zoom and cursors analog video outputs Quad Image BIOS supports VGA, FCode, DVI, and Sync on Green (SOG) An on-board 3.3V regulator can be provided on the PMC and PCI boards for systems which do not supply 3.3V to the backplane. CPCI backplanes always have 3.3V.
Rastergraf Chapter 2 Installing Your Peritek Graphics Board 2.1 Introduction There are 2 steps involved in getting your Rastergraf Graphics board to work in your system: • Unpack and install the Rastergraf graphics board. • Install the software This chapter shows you how to install the Rastergraf graphics board in your computer. Your Rastergraf software User’s Manual (e.g. SDL) provides instructions on how to install the software.
Rastergraf 2.2 Unpacking Your Board When you unpack your board, inspect the contents to see if any damage occurred in shipping. If there has been physical damage, file a claim with the carrier at once and contact Rastergraf for information regarding repair or replacement. Do not attempt to use damaged equipment. Caution Be careful not to remove the board from its antistatic bag or container until you are ready to install it. It is preferable to wear a grounded wrist strap whenever handling computer boards.
Rastergraf 2.3 Preparing for Installation The Eclipse3 includes three different board form factors: PMC, PCI, and CompactPCI. In order to ease the procedure, there follows individual sections that deal with each board type. There really aren’t any model dependencies that affect the board installation. 2.3.1 Interrupt Settings The Eclipse3 boards use the PCI/PMC/CPCI INTA interrupt request line for the particular slot it is plugged into.
Rastergraf 2.3.3 Changing the Jumpers In the following subsections, please refer Figure 2-1 in Section 2.4 for PMC, Figure 2-5 in Section 2.5 for PCI, and Figure 2-7 in Section 2.6 for CompactPCI for to the parts layouts and jumper locations. JP201: VGA PCI Device Jumper JP201 selects the board to respond either as a PCI sub-class “VGA Controller Device” (default) or as an “Other Display Controller” (jumper installed).
Rastergraf 2.4 Eclipse3PMC Graphics Board Installation The Eclipse3PMC board can plug into any 32-bit, 66 MHz, 5V or 3.3V signaling IEEE 1386-2001 compatible single module PMC location. Such locations are most commonly found on VME and CompactPCI computers. The Eclipse3PMC can be installed in PCI and CompactPCI backplanes by using a Rastergraf PMA-P or PMA-C passive bus adapter. Rastergraf also supplies active carriers for PCI, the PMB-P, and a CompactPCI carrier, the PMB-C, which can hold two PMC boards.
Rastergraf Figure 2-1 Jumper Locations for the Fab Rev 1.2 Eclipse3PMC Board JP202 - Reserved JP201 VGA Sub-class Device Enable Fab Revision Number JP203 Optional Local 3.
Rastergraf 2. Open the computer and remove the CPU board onto which the graphics PMC board is to be installed. Identify an empty PMC location (generally there are one or two on a given CPU board). The graphics PMC board is a Universal PMC/PCI device and can be plugged into a PMC port which uses either 5V or 3.3V signaling. 3. Take care to optimize airflow by blocking off unused slots in the card cage, and arrange the boards to permit optimum airflow through them.
Rastergraf Figure 2-3 Installation of a PMC Module into the PMB-C t1 lo CS PM t0 lo CS PM 2-8 Installing Your Peritek Graphics Board
Rastergraf Figure 2-4 Installation of the PMC Module into an Emerson CPV3060 4. Touch a metal part of the computer chassis, remove the graphics board from its anti static bag, and immediately slip it into the slot. After ensuring that the board is seated correctly, install the mounting screws (two near the front and two near the PMC connectors). Note Sometimes the graphics board front panel can hang up going into the carrier front panel hole.
Rastergraf 2.5 Eclipse3PCI Board Installation The Eclipse3PCI board is “Universal PCI” device and is designed to plug into any standard PCI 2.2 specification compatible backplane. Although it is a 32-bit device, it includes the 64-bit expansion connector to take advantage of the extra power and ground pins (no signals are used). It can be plugged into a slot which uses either 5V or 3.3V signaling protocol. Note: The Eclipse3PCI boards require both 3.3V and 5V. Most AT style motherboards do not supply 3.
Rastergraf Figure 2-5 Jumper Locations for the Eclipse3PCI Board 32/64 bit PCI slot JP201 VGA JP101 Flash Bank Fab Revision Number JP233 Local 3.
Rastergraf Caution The static electricity that your body builds up normally can seriously damage the components on the graphics board. 3. Wear a grounded wrist strap and touch a metal part of the computer chassis. Remove the card slot blocking plate from the chassis. Then, remove the graphics board from its anti static bag, and immediately slide it into the slot. Figure 2-6 Installation of a PCI Module into an Emerson MTX 4.
Rastergraf 2.6 Eclipse3CPCI Board Installation The Eclipse3CPCI board can plug into any 32-bit, 5V or 3.3V signaling CompactPCI 3U or 6U slot. Although the board is usually supplied with a 6U faceplate, a 3U faceplate is also available. The board uses only the J1 connector unless the Rear I/O option is included. Installing the Graphics Board Note: Refer to Section 2.3.3 for the settings for JP101, JP102, and JP201. 1. Shut down the operating system and turn off the power.
Rastergraf Figure 2-7 Jumper Locations for the Eclipse3CPCI Board JP201 VGA Fab Revision Number JP101 Flash Bank JP102 Frame/Chassis Ground 2-14 Installing Your Peritek Graphics Board
Rastergraf Caution The static electricity that your body builds up normally can seriously damage the components on the graphics board. 4. Wear a grounded wrist strap. Touch a metal part of the computer chassis, remove the graphics board from its anti static bag, and immediately slide it into the slot. Figure 2-8 Installing a CompactPCI Board 5. After making sure the board is seated correctly, lever the card in with the injector(s) and tighten the screwlock on each end of the faceplate.
Rastergraf 2.7 Finishing the Installation 2.7.1 Connecting to the Monitor If you have an Eclipse3 Standard version board, plug a VGA cable into the VGA compatible front panel connector. If you have an DVI option board, use either a Rastergraf supplied breakout cable or your own cable solution and plug into the DVI-I connector on the graphics board’s front panel. You can use either a VGA (analog) or digital (DVI) compatible monitor.
Rastergraf 2.8 Using an Eclipse3 Board in a PC 2.8.1 Multiboard Operation The Windows 2000 and Windows XP drivers and Linux SDL and X Free 86 4.2 support multihead operation. Single Graphics Board If you are using a PC and the Rastergraf board is to be the system display (and you don't have another VGA controller installed), the system BIOS should find the Rastergraf board, and initialize the display.
Rastergraf x86 Image Features: Support for the 16 standard DOS modes as well as 25 extended VESA modes. See the complete list below. Other extended VESA modes may be added in the future. All standard DOS, VESA and VESA32 functions are supported including DVI, refresh rate, power management and DDC. The Sync-On-Green modes supports the standard DOS modes with "XOR" composite sync and VESA modes with true serrated / equalized composite sync with pedestal.
Rastergraf Table 2-1 x86 Supported Video Modes Type DOS DOS DOS DOS DOS DOS DOS DOS DOS DOS DOS DOS DOS Code 0x00,1 0x02,3 0x04,5 0x06 0x07 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x6A Type VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA VESA Code 0x0100 0x0101 0x0103 0x0105 0x0107 0x0110 0x0111 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118 0x0119 0x011a 0x011b 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 Text 40x25 80x25
Rastergraf 2.9 Using an Eclipse3 Board in a SPARC CPU 2.9.1 Multiboard Operation The Rastergraf loadable DDX module supports multihead operation under Solaris 8 with Xinerama. If you are running on a Sun system, you should have the Rastergraf OpenBoot FCode image loaded into the graphics board. This will enable OpenBoot to correctly identify the graphics board on startup and use it as the console.
Rastergraf 2.9.2.1 Getting Ready to Make the Changes If you are running Solaris, shutdown and halt the CPU until the OpenBoot prompt (ok) appears. Then, disable the CPU from automatically booting until the configuration process is completed: ok setenv auto-boot? false Set the OpenBoot input and output devices to recognize Eclipse. ok setenv input-device keyboard ok setenv output-device screen 2.9.2.
Rastergraf 2.9.2.3 Setting the Console Resolution The initial system default console resolution of the Eclipse3 is 8 bits per pixel, 1152 x 864 @ 60Hz.
Rastergraf 2.9.2.4 Setting the Sync Mode The initial system default sync signal output type of Eclipse3 is separate, positive polarity.
Rastergraf 2.9.2.5 Setting the Console Background and Text Display Appearance The initial system default console background and text display appearance is Black Text on a White Background.. Alternatively, White Text on a Black Background (it will look like this: Eclipse3). To change the appearance, enter the new mode (0 for Black Text, 1 for White Text) in place of the word appear, as shown below.
Rastergraf 2.10 Using an Eclipse3 Board in a PowerPC If the CPU's on-board firmware is VGA aware, it should initialize the graphics board and use it as the system console. However, many PowerPC (PPC) based computers don't have generic VGA support. Newer ones are not "chrp" or "prep" compliant anymore, so they don't know about FCode. Your best bet is to use a board with a VGA BIOS in it.
Rastergraf Chapter 3 Programming On-board Devices 3.1 Introduction This chapter covers the special programming features of the individual devices used on the Eclipse3. It is intended to supply information unique to the board or to the application of a particular chip. Section 1.3 provides a list of appropriate publications that include manufacturer’s data sheets and manuals.
Rastergraf Note Please read these sections before starting on this chapter: Section 1.2 Chapter 2 Functional description of the Eclipse3 boards. Installation This chapter includes the following other sections: 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.
Rastergraf 3.2 Borealis Graphics Accelerator Note The Borealis Technical Manual is available from Rastergraf under NDA. 3.2.1 Introduction This section describes the architecture and includes a block diagram for Borealis high performance graphics controller, which includes a 33/66 MHz PCI compliant interface with no additional external logic required. Please see the following page for a Block Diagram of the Borealis.
Rastergraf Block Diagram Borealis is partitioned into the following functional sections: • • • • • • • Host Bus Interface Aperture Controller Drawing Engine CRT Controller Memory Controller Internal VGA Internal RAMDAC CS[0,2] DQM[15:0] Linear Windows ADR[11:0] Controller WE RAS Display List AD[31:0] Memory SF Processor BE[3:0] CNTRL[6:0] CAS Controller PA[7:0] Host Bus Interface PD[7:0] 2D/3D Drawing CJ[15:0] Engine MCLK HBCLK RST VGA PXD[127:0] HSYNC VSYNC Internal RAMDAC BLANK
Rastergraf 3.2.4 Linear Windows Controller The Linear Windows Controller provides address decoding, address translation, color space conversion between the host interface and the local memory system. It also provides a mechanism for caching reads and writes from the host bus to the local buffers. In write mode, up to eight 32 bit words may be written to the host bus cache. The cache continuously monitors the address of each word written to determine if they are in the same page.
Rastergraf 3.2.6 Display List Processor The Display List Processor (DLP) is used to feed a set of commands to the Drawing Engine. The DLP uses a 128-bit instruction word. The instruction formats allow for each word to write up to three Drawing Engine registers or two text glyphs. There is a four register mode which only writes XY0, XY1, XY2, and XY3. This mode cannot be mixed with any other mode. 3.2.
Rastergraf 3.2.10 Internal RAMDAC and PLL Clock Generators The RAMDAC transforms the raw data from the CRT controller into signals that an analog or digital monitor can understand. In the process, it can add gamma correction and a high resolution cursor. The RAMDAC also provides two programmable clocks which can range from 25 MHz to 250 MHz: one for the memory controller, and the other for the pixel data.
Rastergraf 3.2.11 Coordinate System The screen coordinate system has its origin at the upper left hand corner of the screen, with the X coordinates incrementing left to right and the Y coordinates incrementing top to bottom. The coordinate system for a 1280 by 1024 display is shown in below. (0,0) (0,1023) (1279,0) (1279,1023) Everything performed in X-Y space is done using 16-bit 2's complement integers.
Rastergraf 3.2.12 Borealis Build Options and Power-up Settings The Borealis is a “Plug and Pray” device, whose operation depends on the software. Except as documented in Section 2.3.3, there are no user jumpers. The Technical Manual documents a number of register preloads and functional settings that are determined by 0 ohm resistors installed during manufacturing and read by the Borealis on power up. Note: Software cannot override the values set by the 0 ohm resistors.
Rastergraf 3.3 Borealis Clocks The Eclipse3 boards have several clocks. DECLK is the Borealis Drawing Engine clock and is generated by the CY2292 clock synthesizer. A two frequency select allows the DECLK to be set to 75, 80, 90, or 100 MHz, depending on the operating conditions of the system. The default is 75 MHz. REFCLK is the Borealis PLL reference clock, and is generated by the CY2292 clock synthesizer. It is fixed at 37.5 MHz. LDCLK is generated by the Borealis internal video clock PLL.
Rastergraf 3.4 Synchronous Graphics RAM (SGRAM) The display memory chips are expressly designed for high speed graphics applications. These devices are called Synchronous Graphics RAMs (SGRAMs). The SGRAM replaces the previously used Video RAM, which had a twoport design with separate video output that drove an external RAMDAC. While the VRAM was potentially able to supply substantially better performance than the SGRAM, the price pressures of the PC market made it too expensive.
Rastergraf Display Memory Size The pixel size is programmable to 8, 15, 16, or 32 bpp. The SGRAM on the Borealis is either 16 MB or 32 MB, where a MB = 1024 * 1024 bytes. Calculate the possible display formats based on these values. Note that you can render into SGRAM that is not being used in the active display, and by changing the starting address register in the Borealis pan to it so it is visible or BitBLT the Pixmap data to a static display window. 3.
Rastergraf 3.6 Video Timing Parameters The Borealis must be programmed to generate the proper video timing for the hardware configuration and display format. Rastergraf ’s SDL subroutine library package accepts display format (e.g. 1600 x 1200, 32 bpp) and refresh requirements (e.g. 67 Hz vertical refresh) as parameters to a function call. The software then provides (and loads) a best fit timing profile for the Borealis graphics chip.
Rastergraf 3.6.1 Application Note: Adjusting the Timing Parameters Most monitors have adjustments for Horizontal Frequency, Horizontal Position, Horizontal Size, Vertical Frequency, Vertical Position and Vertical Size. It is recommended that the monitor adjustments be tried before trying monitor settings not in accord with the monitor data sheet. Rastergraf ’s SDL software allows you to define the timing parameters in one of two ways: a) you tell SDL that you are using a multiscan monitor.
Rastergraf Figure 3-3 Video Display Timing Fields Horizontal Border Horizontal Blank Horizontal Retrace Horizontal Blank Active Display Area Horizontal Border Vertical Total Vertical Blanking End Vertical Retrace End Vertical Retrace Start Vertical Blanking Start Vertical Display End Horizontal Total Horizontal Blanking End Horizontal Retrace End Horizontal Retrace Start Horizontal Blanking Start Horizontal Display End Vertical Border Vertical Blank Vertical Retrace Vertical Blank Vertical Border
Rastergraf To change the vertical frequency: The vertical frequency is also known as vertical refresh rate or vertical scan rate. Indications that the vertical frequency needs to be changed are a picture which rolls up or down. Sometimes the appearance is of multiple pictures, one on top of another, with multiple horizontal lines. A very slow vertical frequency will cause the image to flicker. Some monitors display no picture when the vertical frequency is out of its bandwidth.
Rastergraf 3.6.3 Request for Help in Determining Video Timing Values Use the following table to request help when you have a non-standard video timing requirement. Table 3-4 Eclipse3 Video Timing Parameter Request Form Submit to: Rastergraf Technical Support Fax (541) 923-6475 or email: support@rastergraf.
Rastergraf 3.7 System Management Devices and Functions The Eclipse3 Extended Features version boards have devices that are specifically intended to assist in system management. These include: • A National Semiconductor LM75 I2C temperature sensor located near the Borealis chip provides local temperature measurements.
Rastergraf 3.8 Talk To Me Through I2C The Borealis chip has a control register that is used to implement the I2C protocol, a 2 wire serial bus designed Philips Semiconductor. The Borealis is the I2C master and it controls the bus through the DDC control register in the Borealis chip. The I2C bus supports specific “start”, “stop” and “acknowledge” states, so it is possible to probe for these devices and determine whether they exist.
Rastergraf 3.9 DVI Digital Video Output General Description The Thine THC63DV164 transmitter uses DVI® Digital technology to support displays ranging from 640 x 480 up to 1280 x 1024 resolutions in a single link interface. As used on the Eclipse3, the THC63DV164 transmitter is connected to the Borealis using the 24-bit mode, one pixel per clock edge interface. The THC63DV164 is programmed though an I2C slave interface. It supports Receiver and Hot Plug Detection for a variety of power management options.
Rastergraf Figure 3-5 THC63DV164 RGB to 24-bit TMDS Mapping Diagram 24-bit Input Mode (BSEL = 1) DE D[23:0] P0 P1 PN-1 PN IDCK+ DSEL = 0, EDGE = 0 IDCK+ DSEL = 0, EDGE = 1 IDCK+ DSEL = 1 First Latching Edge 24-bit Mode Data Mapping1,2,3 Pin Name D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Notes: P0 R0[7] R0[6] R0[5] R0[4] R0[3] R0[2] R0[1] R0[0] G0[7] G0[6] G0[5] G0[4] G0[3] G0[2] G0[1] G0[0] B0[7] B0[6] B0[5] B0[4] B0[3] B0[2] B0[1] B0[0] P1 R1[7]
Rastergraf 3.10 Flash EEPROM The Eclipse3 has a 128 KB Flash EEPROM. It can be updated in the field using a special updater program. The code in the PROM cannot be directly executed by the CPU. It must be read by the host CPU into its memory and executed from there. The Borealis accesses the PROM data through the Flash EPROM data port. The multiplexed address bits contain both the high and low order address lines for the PROM. The high order lines appear first and so must be latched externally.
Rastergraf Chapter 4 Troubleshooting Introduction This chapter contains information which should assist you in tracking down installation and functional problems with your board. 4.1 General procedures 4.2 Dealing with the PCI bus 4.
Rastergraf 4.1 General Procedures The Eclipse3 boards were designed with reliability and durability in mind. Nevertheless, it may happen that a problem will occur. This section is devoted to aiding the user in tracking down the problem efficiently and quickly. You may be able to locate minor problems without technical assistance. If the problem can not be remedied, Rastergraf can then issue a Return Material Authorization (RMA) so that the board can be returned to the factory for quick repair.
Rastergraf 4.2 Dealing with the PCI Bus Because of the nature of the PCI protocol and the way support has been implemented in the Operating Systems for PCI bus devices such as the Eclipse3, it is not possible to follow the same debugging strategies. In fact, there are no address jumpers for these boards. Everything is configured in software through a set of on-board registers, which control the characteristics of the board as required by the PCI Specification.
Rastergraf defective in proper usage. This warranty does not apply to modules which have been subjected to mechanical abuse, electrical abuse, overheating, or other improper usage. This warranty is made in lieu of all other warranties expressed or implied. All warranty repair work will be done at the Rastergraf factory. Return Policy Before returning a module the customer must first request a Return Material Authorization (RMA) number from the factory.
Rastergraf Index 5 wire VGA monitors, 2-16 ACE Series, 0-1, 1-1, 1-2, 1-5, 1-8, 1-9, 110, 1-14, 1-23, 1-24, 2-3, 2-4, 2-5, 2-6, 210, 2-11, 2-13, 2-14, 2-16, 2-17, 2-20, 3-1, 3-2, 3-10, 3-12, 3-13, 3-17, 3-18, 3-19, 320, 3-22, 4-2, 4-3 Additional References, 1-7 Adjusting the Video Timing, 3-14 Aperture controller, 3-4 AT24C02, 1-11, 3-19, 3-22 Aurora3, 0-1 Checking your Display, 2-16 color register, 3-11 CompactPCI, 0-1, 1-1, 1-2, 1-11, 2-3, 2-5, 2-13, 2-14, 2-15 Configuration Information, 1-24 conventions
