User`s manual

Rastergraf
3-6 Programming On-board Devices
3.2.6 Display List Processor
The Display List Processor (DLP) is used to feed a set of commands to the
Drawing Engine. The DLP uses a 128-bit instruction word. The instruction
formats allow for each word to write up to three Drawing Engine registers
or two text glyphs. There is a four register mode which only writes XY0,
XY1, XY2, and XY3. This mode cannot be mixed with any other mode.
3.2.7 CRT Controller
The CRT Controller provides programmable CRT timing signals:
horizontal, vertical blanks and syncs. It is also responsible for generating
requests to the memory controller for screen refresh cycles. A free running
frame counter which generates interrupts to the Host is also provided. This
is useful for synchronizing bit map copies. CRT Controller also provides
display refresh data for the internal RAMDAC.
3.2.8 Memory Controller
The Memory Controller arbitrates and controls all access to the local
memory buffer by the Host Interface, the CRT controller, and the Drawing
Engine. This unit provides support for SGRAM memory.
3.2.9 VGA Core
The Borealis incorporates an IBM-compatible VGA core. The VGA core
implements the standard VGA register set for the various VGA
components (CRT controller, sequencer, graphics controller, attribute
controller, etc.) and is capable generating the standard VGA modes (00h -
07h, 00h - 13h). The control of memory and CRT signals can be switched
between the VGA core and the Borealis. The VGA memory space is
shared with the Borealis frame buffer and is sparsely mapped within it.