User`s manual

Rastergraf
3-10 Programming On-board Devices
3.3 Borealis Clocks
The Eclipse3 boards have several clocks.
DECLK is the Borealis Drawing Engine clock and is generated by the
CY2292 clock synthesizer. A two frequency select allows the DECLK to
be set to 75, 80, 90, or 100 MHz, depending on the operating conditions of
the system. The default is 75 MHz.
REFCLK is the Borealis PLL reference clock, and is generated by the
CY2292 clock synthesizer. It is fixed at 37.5 MHz.
LDCLK is generated by the Borealis internal video clock PLL. It is an
auxiliary clock output (from the Borealis) and is used as the pixel clock
for the digital output. One pixel is output for each edge of LDCLK.
SECLK is the Borealis Setup Engine clock. Its source is selected under
program control using a register in the Borealis. The choices include the
PCI bus clock and MCLK/2.
VCLK is the Borealis video (pixel) clock and is generated by a PLL
internal to the Borealis. It uses the REFCLK as its PLL reference. The
pixel frequency can be set to between 25 MHz and 250 MHz.
MCLK is the Borealis memory clock for the Borealis memory controller
and SGRAM interface. and is generated by a independent PLL internal to
the Borealis. It uses the REFCLK as its PLL reference. The frequency can
be set to between 25 MHz and 250 MHz, although the usable memory
frequency limit is about 125 MHz.
When the Eclipse3 powers up, MCLK is REFCLK and VCLK is
undefined. Once the VGA BIOS (or, if in a non-PC environment, the
Eclipse3 graphics software) is executed, the MCLK and VCLK PLLs can
be programmed to select higher frequencies in accordance to the desired
display format and memory timing.
A consequence of the multi-clock nature of the Borealis is that if you read
a register driven by the pixel clock (e.g. VCOUNT), you may get erratic
results because the host bus interface uses a different clock. You have to
read the register twice, read the comparison flag or use interrupts to get
correct results. The reason for this is simple: the VCOUNT register can
change state in the middle of a Borealis host read cycle. Its operations are
totally asynchronous to the Borealis PCI bus interface clock.