User's Manual
Table Of Contents
- General Description
- Features
- System Applications
- Block Diagram
- Pin Assignments
- Pin Descriptions
- CPU Access to Endpoint Data
- USB Request
- Get Descriptor-Device
- Get Descriptor-Device Qualifier (High Speed)
- Get Descriptor-Configuration
- Get Descriptor-String Index 0
- Get Descriptor-String Index 1
- Get Descriptor-String Index 2
- Get Descriptor-String Index 3
- Get Descriptor-String Index 4
- Get Descriptor-String Index 5
- Get Descriptor-Other Speed Configuration
- Set Address
- Set Interface 0
- Set Feature Device
- Clear Feature Device
- Set Config 0
- Set Config 1
- EEPROM (93C46 or 93C56) Contents
- USB Packet Buffering
- Functional Description
- Application Diagram
- Electrical Characteristics
- Mechanical Dimensions
- Ordering Information
RTL8187L
Datasheet
Wireless LAN Network Interface Controller 9 Track ID JATR-1076-21 Rev. 1.2
7. CPU Access to Endpoint Data
7.1.
Control Transfer
Control transfers configure and send commands to a device. Because they are so important, they employ
extensive USB error checking. The host reserves a portion of each USB frame for control transfers. Control
transfers consist of two or three stages. The SETUP stage contains eight bytes of USB control data. An
optional DATA stage contains more data, if required. The STATUS stage allows the device to indicate
successful completion of a control operation.
7.2.
Bulk Transfer
Bulk data is bursty, traveling in packets of 8, 16, 32, or 64 bytes at full speed, or at 512 bytes at high speed.
Bulk data has guaranteed accuracy due to an automatic retry mechanism for erroneous data. The host
schedules bulk packets when there is available bus time.