User's Manual

RTL8187L
Datasheet
Wireless LAN Network Interface Controller 21 Track ID JATR-1076-21 Rev. 1.2
10. USB Packet Buffering
The RTL8187L incorporates two independent FIFOs for transferring data to/from the system interface and
from/to the network. The FIFOs provide temporary storage of data, freeing the host system from the
real-time demands of the network.
The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the
Receive Configuration registers. These values determine how full or empty the FIFOs must be before the
device requests the bus. Once the RTL8187L requests the bus, it will attempt to empty or fill the FIFOs as
allowed by the respective MXDMA settings in the Transmit Configuration and Receive Configuration
registers.
10.1. Transmit Buffer Manager
The buffer management scheme used on the RTL8187L allows quick, simple, and efficient use of the frame
buffer memory. The buffer management scheme uses separate buffers and descriptors for packet
information. This allows effective transfers of data to the transmit buffer manager by simply transferring
the descriptor information to the transmit queue.
The Tx Buffer Manager DMA’s packet data from system memory and places it in the 3.5KB transmit FIFO,
and pulls data from the FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO,
allowing packets to be transmitted with Short InterFrame (SIF) space. Additionally, once the RTL8187L
requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting.
The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by
drawing from two separate descriptor lists to fill the internal FIFO. If packets are available in the high
priority queues, they will be loaded into the FIFO before those of low priority.
10.2. Receive Buffer Manager
The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer
Manager retrieves packet data from the Rx MAC and places it in the 4KB receive data FIFO, and pulls data
from the FIFO for DMA to system memory. The receive FIFO is controlled by the FIFO threshold value in
RXFTH. This value determines the number of long words written into the FIFO from the MAC unit before
a DMA request for system memory occurs. Once the RTL8187L gets the bus, it will continue to transfer the
long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the
packet, or the max DMA burst size is reached, as set in MXDMA.
10.3. Packet Recognition
The Rx packet filter and recognition logic allows software to control which packets are accepted, based on
destination address and packet type. Address recognition logic includes support for broadcast, multicast
hash, and unicast addresses. The packet recognition logic includes support for WOL and programmable
pattern recognition.