User's Manual
Table Of Contents
- General Description
- Features
- System Applications
- Block Diagram
- Pin Assignments
- Pin Descriptions
- CPU Access to Endpoint Data
- USB Request
- Get Descriptor-Device
- Get Descriptor-Device Qualifier (High Speed)
- Get Descriptor-Configuration
- Get Descriptor-String Index 0
- Get Descriptor-String Index 1
- Get Descriptor-String Index 2
- Get Descriptor-String Index 3
- Get Descriptor-String Index 4
- Get Descriptor-String Index 5
- Get Descriptor-Other Speed Configuration
- Set Address
- Set Interface 0
- Set Feature Device
- Clear Feature Device
- Set Config 0
- Set Config 1
- EEPROM (93C46 or 93C56) Contents
- USB Packet Buffering
- Functional Description
- Application Diagram
- Electrical Characteristics
- Mechanical Dimensions
- Ordering Information
RTL8187L
Datasheet
Wireless LAN Network Interface Controller 2 Track ID JATR-1076-21 Rev. 1.2
2. Features
128-Pin LQFP and 128-pin LQFP Lead
(Pb)-Free package
State machine implementation without
external memory (RAM, flash) requirement
Complies with IEEE 802.11a/b/g standards
Supports descriptor-based buffer
management
Integrated Wireless LAN MAC and Direct
Sequence Spread Spectrum/OFDM
Baseband Processor in one chip
Enhanced signal detector, adaptive frequency
domain equalizer, and soft-decision Viterbi
decoder to alleviate severe multipath effects
Processing Gain compliant with FCC
On-Chip A/D and D/A converters for I/Q
Data, AGC, and Adaptive Power Control
Supports both transmit and receive Antenna
Diversity
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, and 54Mbps
Supports 40MHz OSC as the internal clock
source. The frequency deviation of the OSC
must be within 25 PPM on IEEE 802.11g and
20 PPM on IEEE 802.11a
IEEE 802.11g protection mechanisms for
both RTS/CTS and CTS-to-self
Burst-mode support for dramatically
enhanced throughput
DSSS with DBPSK and DQPSK, CCK
modulations and demodulations supported
with long and short preamble
OFDM with BPSK, QPSK, 16QAM and
64QAM modulations and demodulations
supported with rate compatible punctured
convolutional coding with coding rate of 1/2,
2/3, and 3/4
Efficient IQ-imbalance calibration, DC
offset, phase noise, frequency offset and
timing offset compensation reduce analog
front-end impairments
Selectable digital transmit and receiver FIR
filters provided to meet transmit spectrum
mask requirements and to reject adjacent
channel interference
Programmable scaling both in transmitter
and receiver to trade quantization noise
against the increased probability of clipping
Fast receiver Automatic Gain Control (AGC)
& antenna diversity functions
Hardware-based IEEE 802.11i
encryption/decryption engine, including
64-bit/128-bit WEP, TKIP, and AES
Supports Wi-Fi alliance WPA and WPA2
security
Contains two large independent transmit and
receive FIFO buffers
Advanced power saving mode when the
LAN and wakeup function are not used
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource
configuration and ID parameter data
LED pins for various network activity
indications
Two GPIO pins supported